Table of Contents
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Table 14-1 describes each signal; detailed descriptions can be found in subsequent sections.
Signal
Pins Active I/O
A[0Ð31]
32
High
Address Bus
RD/WR
1
High
Read/Write
MOTOROLA
A[0Ð31]
32
R/W
1
BURST
1
TSIZ[0Ð1]
2
AT[0Ð3]
4
PTR
1
RSV
1
STS
1
BDIP
1
TS
1
KR/RETRY
1
CR
1
D[0Ð31]
32
DP[0Ð3]
4
BI
1
TA
1
TEA
1
BR
1
BG
1
BB
1
Figure 14-2. MPC860 Bus Signals
Table 14-1. MPC860 Signal Overview
Address and Transfer Attributes
O
Driven by the MPC860 when it owns the external bus. SpeciÞes the physical
address of the bus transaction. Can change during a transaction when controlled
by the memory controller.
I
Sampled by the MPC860 when an external device initiates a transaction and the
memory controller was conÞgured to handle external master accesses.
O
Driven by the MPC860 along with the address when it owns the external bus.
Driven high indicates that a read access is in progress. Driven low indicates that a
write access is in progress.
I
Sampled by the MPC860 when an external device initiates a transaction and the
memory controller was conÞgured to handle external master accesses.
Chapter 14. MPC860 External Bus Interface
Part IV. Hardware Interface
Address
and
Transfer
Attributes
Transfer
Start
Reservation
Protocol
Data
Transfer
Cycle
Termination
Arbitration
Description
14-3
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