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Chapter 16
Memory Controller
160
160
The memory controller is responsible for controlling a maximum of eight memory banks
shared between a general-purpose chip-select machine (GPCM) and a pair of sophisticated
user-programmable machines (UPMs). It supports a glueless interface to SRAM, EPROM,
ßash EPROM, regular DRAM devices, self-refresh DRAMs, extended data output DRAM
devices, synchronous DRAMs, and other peripherals. This ßexible memory controller
allows the implementation of memory systems with very speciÞc timing requirements.
The GPCM provides interfacing for simpler, lower-performance memory resources and
memory-mapped devices. The GPCM has inherently lower performance because it does
not support bursting. For this reason, GPCM-controlled banks are used primarily for
boot-loading and access to nonburstable memory-mapped peripherals.
The UPM provides both more features and, because it supports bursting, higher
performance. Therefore it is typically used to interface with higher-performance run-time
memory such as DRAM and bursting SRAM.
The UPM supports address multiplexing of the external bus, periodic timers, and
generation of programmable control signals for row address and column address strobes to
allow for a glueless interface to DRAM devices. The periodic timers allow refresh cycles
to be initiated while the address MUXing provides row and column addresses.
Different timing patterns can be generated for the control signals that govern a memory
device. These patterns deÞne how the external control signals behave in read-access,
write-access, burst read-access, or burst write-access requests. Periodic timers are also
available to periodically generate user-deÞned refresh cycles.
16.1 Features
The following is a list of the memory controllerÕs main features:
¥ Eight memory banks
Ñ 32-bit address decode with mask
Ñ Variable block sizes (32 Kbytes to 4 Gbytes)
Ñ Byte parity generation/checking
MOTOROLA
Chapter 16. Memory Controller
16-1
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