Motorola MPC860 PowerQUICC User Manual page 41

Figure
Number
16-19 GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1,
TRLX = 0) ....................................................................................................... 16-21
GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1,
16-20
TRLX = 0) ....................................................................................................... 16-22
16-21 GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, and
TRLX = 1) ....................................................................................................... 16-22
16-22 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,
TRLX = 1) ....................................................................................................... 16-23
16-23 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1,
TRLX =1) ........................................................................................................ 16-24
16-24 GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1,
TRLX =1) ........................................................................................................ 16-24
16-25 GPCM Read Followed by Write (EHTR = 0) ................................................. 16-25
16-26 GPCM Write Followed by Read (EHTR = 1) ................................................. 16-26
16-27 GPCM Read Followed by Read from Different Banks (EHTR = 1)............... 16-26
16-28 GPCM Read Followed by Read from Same Bank (EHTR = 1) ...................... 16-27
16-29 Asynchronous External Master Configuration for GPCM-Handled
Memory Devices.............................................................................................. 16-28
16-30 Asynchronous External Master, GPCM-Handled Memory Access
Timing (TRLX = 0) ......................................................................................... 16-29
16-31 User-Programmable Machine Block Diagram................................................. 16-30
16-32 RAM Array Indexing....................................................................................... 16-31
16-33 Memory Periodic Timer Request Block Diagram ........................................... 16-32
16-34 UPM Clock Scheme One (Division Factor = 1) .............................................. 16-33
16-35 UPM Clock Scheme Two (Division Factor = 2) ............................................. 16-33
16-36 UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) ......... 16-34
16-37 UPM Signals Timing Example Two (Division Factor = 2, EBDF = 01) ........ 16-35
16-38 RAM Array and Signal Generation ................................................................. 16-35
16-39 The RAM Word ............................................................................................... 16-36
16-40 .CS Signal Selection......................................................................................... 16-39
16-41 BS Signal Selection.......................................................................................... 16-40
16-42 Early GPL5 Control ......................................................................................... 16-41
16-43 Address Multiplex Timing............................................................................... 16-44
16-44 UPM Read Access Data Sampling .................................................................. 16-48
16-45 Wait Mechanism Timing for Internal and External Synchronous Masters ..... 16-49
16-46 Wait Mechanism Timing for an External Asynchronous Master .................... 16-50
16-47 Synchronous External Master Access.............................................................. 16-53
16-48 Asynchronous External Master Access ........................................................... 16-54
16-49 Synchronous External Master Interconnect Example...................................... 16-55
16-50 Synchronous External Master: Burst Read Access to Page Mode DRAM ..... 16-56
16-51 Asynchronous External Master Interconnect Example.................................... 16-57
16-52 Asynchronous External Master Timing Example............................................ 16-58
16-53 Page-Mode DRAM Interface Connection ....................................................... 16-59
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