Motorola MPC860 PowerQUICC User Manual page 67

portsÑA, B, C, and D. Each signal in the I/O ports can be conÞgured as a
general-purpose I/O signal or as a signal dedicated to supporting
communications devices, such as SMCs and SCCs.
Ñ Chapter 35, ÒCPM Interrupt Controller,Ó describes how the CPM interrupt
controller (CPIC) accepts and prioritizes the internal and external interrupt
requests from the CPM blocks and passes them to the system interface unit
(SIU). The CPIC also provides a vector during the core interrupt acknowledge
cycle.
Ñ Chapter 36, ÒDigital Signal Processing,Ó describes the CPMÕs hardware and
library functions that support DSP applications.
¥ Part VI, ÒDebug and Test,Ó describes how to use the MPC860 facilities for
debugging and system testing.
Ñ Chapter 37, ÒSystem Development and Debugging,Ó describes support provided
for program ßow tracking, internal watchpoint and breakpoint generation, and
emulation systems control.
Ñ Chapter 38, ÒIEEE 1149.1 Test Access Port,Ó describes the dedicated user-
accessible test access port (TAP), which is fully compatible with the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture.
¥ Appendix A, ÒByte Ordering,Ó discusses the MPC860 implementation of little- and
big-endian byte mapping.
¥ Appendix B, ÒSerial Communications Performance,Óprovides insight in
maximizing performance of MPC860-based systems.
¥ Appendix C, ÒRegister Quick Reference Guide,Ó contains a quick reference guide to
the MPC860 registers.
¥ Appendix D, ÒMPC860 Instruction Set Listings,Ó contains tables of the PowerPC
instructions supported by the MPC860.
¥ This manual also includes a glossary and an index.
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