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Figure
Number
18-7
Timer Reference Registers (TRR1ÐTRR4) ..................................................... 18-10
18-8
Timer Capture Registers (TCR1ÐTCR4) ......................................................... 18-10
18-9
Timer Capture Registers (TCR1ÐTCR4) ......................................................... 18-11
18-10
Timer Event Registers (TER1ÐTER4)............................................................. 18-11
19-1
Communications Processor (CP) Block Diagram.............................................. 19-2
19-2
RISC Controller Configuration Register (RCCR) ............................................. 19-4
19-3
CP Command Register (CPCR)......................................................................... 19-6
19-4
Dual-Port RAM Block Diagram ........................................................................ 19-9
19-5
Dual-Port RAM Memory Map......................................................................... 19-10
19-6
RISC Timer Table RAM Usage....................................................................... 19-13
19-7
RISC Timer Command Register (TM_CMD) ................................................. 19-14
19-8
RISC Timer Event Register (RTER)/Mask Register (RTMR) ........................ 19-15
20-1
MPC860 SDMA Data Paths .............................................................................. 20-1
20-2
SDMA U-Bus Arbitration (Cycle Steal)............................................................ 20-3
20-3
SDMA Configuration Register (SDCR) ............................................................ 20-4
20-4
SDMA Status Register (SDSR) ......................................................................... 20-4
20-5
DMA Channel Mode Register (DCMR)............................................................ 20-7
20-6
IDMA Status Registers (IDSR1/IDSR2) ........................................................... 20-8
20-7
IDMAx ChannelÕs BD Table ............................................................................. 20-9
20-8
IDMA Buffer Descriptor Structure.................................................................. 20-10
20-9
Function Code RegistersÑSFCR and DFCR .................................................. 20-11
20-10
SDACK Timing Diagram: Single-Address
Peripheral Write, Externally-Generated TA..................................................... 20-16
20-11
SDACK Timing Diagram: Single-Address
Peripheral Write, Internally-Generated TA...................................................... 20-17
20-12
SDACK Timing Diagram: Single-Address
Peripheral Read, Internally-Generated TA....................................................... 20-18
20-13
IDMA Channel Mode Register (DCMR) (Single-Buffer Mode) .................... 20-19
20-14
IDMA1 Status Register (IDSR1) (Single-Buffer Mode) ................................. 20-20
20-15
Single-Address IDMA1 Burst Timing (Single-Buffer Mode)......................... 20-21
21-1
MPC860 SI Block Diagram ............................................................................... 21-2
21-2
Various Configurations of a TDM Channel....................................................... 21-5
21-3
Dual TDM Channel Example ............................................................................ 21-6
21-4
Enabling Connections through the SI ................................................................ 21-8
21-5
SI RAM Partitioning Using TDMa with Static Frames..................................... 21-9
21-6
SI RAMÑTwo TDMs with Static Frames ...................................................... 21-10
21-7
SI RAM Dynamic Changes with TDMa and TDMb ....................................... 21-12
21-8
SI RAM Partitioning Using TDMa with Dynamic Frames ............................. 21-13
21-9
SI RAM Partitioning Using Two TDMs with Dynamic Frames ..................... 21-13
21-10
SIRAM Entry ................................................................................................... 21-14
21-11
Example Using SI RAMn[SWTR] .................................................................. 21-15
21-12
SI Global Mode Register (SIGMR) ................................................................. 21-17
21-13
SI Mode Register (SIMODE) .......................................................................... 21-18
MOTOROLA
ILLUSTRATIONS
Title
Illustrations
Page
Number
xliii
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