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GCLK1
GCLK2
GCLK1_50
(EBDF=00)
GCLK2_50
(EBDF=00)
CLKOUT
(EBDF=00)
GCLK1_50
(EBDF=01)
GCLK2_50
(EBDF=01)
CLKOUT
(EBDF=01)
Figure 15-9. Memory Controller and External Bus Clocks Timing Diagram for
(CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0)
The frequency of GCLK1_50 and GCLK2_50 are effected both by the SCCR[DFNH] and
SCCR[DFNL] dividers and by the SCCR[EBDF] divider. Thus, the frequency for
GCLKx_50 and CLKOUT is:
VCOOUT
----------------------------------------------------------------
GCLKx_50
=
freq
DFNH
(
)or 2
2
CLKOUT is the only externally visible clock, and is equivalent to the internal signal
GCLK2_50. CLKOUT can drive at full-strength, half-strength, or it can be disabled. The
strength of the drive is controlled in the system clock and reset control register. Disabling
or decreasing the strength of CLKOUT reduces power consumption, noise, and
electromagnetic interference on the printed circuit board. While the SPLL is acquiring lock,
the CLKOUT signal does not oscillate and remains in a low state.
MOTOROLA
1
freq
´
---------------------------
DFNL 1
+
EBDF 1
+
(
)
Chapter 15. Clocks and Power Control
Part IV. Hardware Interface
15-13
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