Motorola MPC860 PowerQUICC User Manual page 199

8.2 Data Cache Organization
The data cache is organized as 128 sets of two blocks as shown in Figure 8-2. Each block
consists of 16 bytes, two state bits, a lock bit, and an address tag.
0
21
set0
set1
set126
set127
MMU
COMP
hit0
Each cache block contains four contiguous words from memory that are loaded from a
four-word boundary (that is, bits A[28Ð31] of the logical (effective) addresses are zero); as
a result, cache blocks are aligned with page boundaries. Note that address bits A[21Ð27]
MOTOROLA
Data effective address
way0
tag0 w0 w1 w2 w3 w2
tag1 w0 w1 w2 w3
tag126 w0 w1 w2 w3
tag127 w0 w1 w2 w3
21
HIT
Figure 8-2. Data Cache Organization
Chapter 8. Instruction and Data Caches
Part II. PowerPC Microprocessor Module
20 21
7
. . . .
tag0
. . . .
tag1
L
R
U
A
r
r
a
y
. . . .
tag126
. . . .
tag127
128
COMP
hit1
Bidirectional multiplexer 2 -> 1
128
To/from block buffer
To/from burst buffer
27 28 31
4
Byte select
way1
w0 w1 w2 w3 w2
w0 w1 w2 w3
w0 w1 w2 w3
w0 w1 w2 w3
21
128
8-5