Motorola MPC860 PowerQUICC User Manual page 634

Part V. The Communications Processor Module
Associated with each SCC is a digital phase-locked loop (DPLL) for external clock
recovery, which supports NRZ, NRZI, FM0, FM1, Manchester, and Differential
Manchester. If the clock recovery function is not required (that is, synchronous
communication), then the DPLL can be disabled, in which case only NRZ and NRZI are
supported.
An SCC can be connected to its own set of pins on the MPC860. This conÞguration is called
the non-multiplexed serial interface (NMSI) and is described in Chapter 21, ÒSerial
Interface.Ó Using NMSI, an SCC can support standard modem interface signals, RTS, CTS,
and CD, through the port C pins and the CPM interrupt controller (CPIC). If required,
software and additional parallel I/O lines can be used to support additional handshake
signals. Figure 22-1 shows the SCC block diagram.
Modem Lines
RXD Decoder
22.1 Features
The following is a list of the main SCC features. (Performance Þgures assume a 25-MHz
system clock.)
¥ Implements HDLC/SDLC, HDLC bus, asynchronous HDLC, BISYNC,
synchronous start/stop, asynchronous start/stop (UART), AppleTalk/LocalTalk, and
totally transparent protocols
¥ Supports 10-Mbps Ethernet/IEEE 802.3 (half- or full-duplex)
¥ Additional protocols supported through Motorola-supplied RAM microcodes:
ProÞbus, Signaling System#7 (SS7), ATM over T1/E1 (ATOM1)
¥ Additional protocols can be added in the future through the use of RAM microcodes.
22-2
60x Bus
Control
Registers
Peripheral Bus
Rx
Data
Rx
FIFO
Control
Unit
Delimiter Shifter
Figure 22-1. SCC Block Diagram
MPC860 PowerQUICC UserÕs Manual
DPLL
and Clock
Recovery
Clock
Generator
Internal Clocks
Tx
Data
Tx
FIFO
Control
Unit
Shifter Delimiter
TCLK
RCLK
Modem Lines
Encoder TXD
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