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28.22 SCC Ethernet Programming Example
The following is an initialization sequence for the SCC1 in Ethernet mode. The CLK1 pin
is used for the Ethernet receiver and CLK2 is used for the transmitter.
1. ConÞgure port A to enable TXD1 and RXD1. Set PAPAR[14, 15] and clear
PADIR[14, 15] and PAODR[14].
2. ConÞgure port C to enable CTS1 (CLSN) and CD1 (RENA). Clear PCPAR[10, 11]
and PCDIR[10, 11] and set PCSO[10, 11].
3. Do not enable the RTS1 (TENA) pin yet because it is still functioning as RTS and
transmission on the LAN could begin accidentally.
4. ConÞgure port A to enable the CLK1 and CLK2 pins. Set PAPAR[6, 7] and clear
PADIR[6, 7].
5. Connect CLK1 and CLK2 to SCC1 using the serial interface. Set SICR[R1CS] to
0b101 and SICR[T1CS] to 0b100.
6. Connect the SCC1 to the NMSI and clear SICR[SC1].
7. Initialize the SDMA conÞguration register (SDCR) to 0x0001.
8. Write RBASE and TBASE in the SCC1 parameter RAM to point to the RxBD and
TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port
RAM and one TxBD following that RxBD, write RBASE with 0x0000 and TBASE
with 0x0008.
9. Program the CPCR to execute an
channel.
10. Write RFCR and TFCR with 0x10 for normal operation.
11. Write MRBLR with the maximum number of bytes per receive buffer. Here, assume
1520 bytes, so MRBLR = 0x05F0. In this example, the user wants to receive an
entire frame into one buffer, so MRBLR is the Þrst value larger than 1518 evenly
divisible by four.
12. Write C_PRES with 0xFFFF_FFFF to comply with 32-bit CCITT-CRC.
13. Write C_MASK with 0xDEBB_20E3 to comply with 32-bit CCITT-CRC.
14. Clear CRCEC, ALEC, and DISFC for clarity.
15. Write PAD with 0x8888 for the PAD value.
16. Write RET_LIM with 0x000F.
17. Write MFLR with 0x05EE to make the maximum frame size 1518 bytes.
18. Write MINFLR with 0x0040 to make the minimum frame size 64 bytes.
19. Write MAXD1 and MAXD2 with 0x05F0 to make the maximum DMA count 1520
bytes.
20. Clear GADDR1ÐGADDR4. The group hash table is not used.
21. Write PADDR1_H with 0x0380, PADDR1_M with 0x12E0, and PADDR1_L with
0x5634 to conÞgure the physical address 0x8003_E012_3456.
MOTOROLA
Part V. The Communications Processor Module
INIT RX AND TX PARAMETERS
Chapter 28. SCC Ethernet Mode
command for this
28-27
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