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Part IV. Hardware Interface
The MPC860Õs address bus speciÞes the address for the transfer and its data bus transfers
the data. Control signals indicate the beginning of the cycle and the type of cycle, as well
as the address space and size of the transfer. The selected device controls cycle length with
signal(s) used to terminate the cycle. A strobe signal for the address bus indicates the
validity of the address and gives data timing information. The MPC860 bus is synchronous,
therefore, the bus and control input signals must be timed to setup and hold times relative
to the rising edge of the clock. At minimum, single-beat bus cycles can be completed in two
clock cycles.
Furthermore, for all inputs, the MPC860 latches the inputÕs level during a sample window,
shown in Figure 14-1, around the rising clock edge. To ensure that an input signal is
recognized on a speciÞc rising clock edge, that input must be stable during the sample
window. If an input changes during the window, the level recognized by the MPC860 is
unpredictable; however, the MPC860 always resolves the latched level to either a logical
high or low before using it. For deterministic operation, all input signals must obey the
protocols described in this chapter in addition to meeting input setup and hold times.
Input Hold Time
Input Setup Time
Clock
Signal
Sample
Window
Figure 14-1. Input Sample Window
TSIZ0 and TSIZ1 indicate the number of bytes remaining to be transferred during an
operand cycle (consisting of one or more bus cycles) and are driven with the address type
signals at the beginning of a bus cycle. These signals are valid at the rising edge of the clock
in which the transfer start signal (TS) is asserted.
14.3 Bus Interface Signal Descriptions
Figure 14-2 shows the bus signals for the MPC860.
14-2
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
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