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Chapter 14
MPC860 External Bus Interface
140
140
The MPC860 bus is a synchronous, burstable bus that can support multiple masters. Signals
driven on this bus are required to make the setup and hold time relative to the bus clockÕs
rising edge. The MPC860 architecture supports byte, half-word, and word operands
allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles
controlled by the size outputs (TSIZ0, TSIZ1). Access to 16- and 8-bit ports is done for
slaves controlled by the memory controller.
14.1 Features
The MPC860 bus interface features are listed as follows:
¥ 32-bit address bus with transfer size indication
¥ 32-bit data bus
¥ Dynamic bus sizing to 32-, 16-, or 8-bit ports accessed through the memory
controller
¥ TTL-compatible interface
¥ Bus arbitration supported optionally by internal or external logic
¥ Bus arbitration logic on-chip supports an external master with programmable
priority
¥ Compatible with PowerPC architecture
¥ Easy to interface to slave devices
¥ Bus is synchronous (all signals are referenced to rising edge of bus clock)
¥ Contains support for data parity
14.2 Bus Transfer Overview
The bus transfers information between the MPC860 and external memory or a peripheral
device. External devices can accept or provide 8, 16, and 32 bits in parallel and must follow
the handshake protocol described in this section. The maximum number of bits accepted or
provided during a bus transfer is deÞned as port width.
MOTOROLA
Chapter 14. MPC860 External Bus Interface
14-1
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