Table of Contents
Advertisement
BRGOx
(Output is CLKx Input)
TXD
(Output is RXD Input)
RTS
(Output is CD Input)
Notes:
1. Each MPC860 generates its own transmit clocks. If the transmit and receive clocks are the same, one MPC860 can generate transmit and
receive clocks for the other MPC860. For example, CLKx on MPC860(B) could be used to clock the transmitter and receiver.
2. CTS should be configured as always asserted in the Port C parallel I/O or connected to ground externally.
3. The required GSMR configurations are DIAG= 00, CTSS=1, CTSP is a ÒdonÕt careÓ, CDS=1, CDP=0, TTX=1, and TRX=1. REVD and TCRC
are application-dependent.
4. The transparent frame contains a CRC if TxBD[TC] is set.
Figure 29-1. Sending Transparent Frames between MPC860
MPC860(A) and MPC860(B) exchange transparent frames and synchronize each other
using RTS and CD. However, CTS is not required because transmission begins at any time.
Thus, RTS is connected directly to the other MPC860 CD pin. GSMR_H[RSYN] is not
used and transmission and reception from each MPC860 are independent.
29.4.1.3 Transparent Mode without Explicit Synchronization
If there is no need to synchronize the transparent controller at a speciÞc point, the user can
ÔfakeÕ synchronization in one of the following ways:
¥ Tie a parallel I/O pin to the CTS and CD lines. Then, after enabling the receiver and
transmitter, provide a falling edge by manipulating the I/O pin in software.
¥ Enable the receiver and transmitter for the SCC in loopback mode and then change
GSMR_L[DIAG] to 0b00 while the transmitter and receiver and enabled.
29.4.1.4 End of Frame Detection
An end of frame cannot be detected in the transparent data stream since there is no deÞned
closing ßag in transparent mode. Therefore, if framing is needed, the user must use the CD
line to alert the transparent controller of an end of frame.
MOTOROLA
MPC860 (A)
TXD
RTS
BRGOx
RXD
CD
CLKx
First Bit of Frame Data
CD Lost Condition Terminates Reception of Frame
Chapter 29. SCC Transparent Mode
Part V. The Communications Processor Module
MPC860 (B)
RXD
CD
CLKx
TXD
RTS
BRGOx
Last Bit of Frame Data
or CRC
TxBD[L] = 1 Causes Negation of RTS
29-5
Advertisement
Table of Contents
