Motorola MPC860 PowerQUICC User Manual page 910

Part V. The Communications Processor Module
Table 35-3. CICR Field Descriptions (Continued)
Bits Name
19Ð23 HP Highest priority. SpeciÞes the 5-bit interrupt number of the CPIC interrupt source that is advanced to
the highest priority in the table. These bits can be modiÞed dynamically. (Programming HP =
0b11111 keeps PC15 the highest priority source for external interrupts to the core.)
24 IEN Interrupt enable. Master enable for CPM interrupts.
0 CPM interrupts are disabled
1 CPM interrupts are enabled
25Ð30 Ñ Reserved
31 SPS Spread priority scheme. Selects the relative priority scheme; cannot be changed dynamically.
0 Grouped. The SCCs are grouped by priority at the top of the table.
1 Spread. The SCCs are spread by priority in the table.
1
Note: Do not program the same SCC to more than one priority position (a, b, c, or d). These bits can be changed
dynamically.
35.5.2 CPM Interrupt Pending Register (CIPR)
Each bit in the read/write CPM interrupt pending register (CIPR) corresponds to a CPM
interrupt source. The CPIC sets the appropriate CIPR bit when a CPM interrupt is received.
Names and placement of bits, shown in Figure 35-4, are identical in the CIPR, CIMR, and
CISR, and they follow the priorities described in Table 35-1.
Bit 0 1 2
Field PC15 SCC1 SCC2
Reset
R/W
Addr
Bit 16 17 18
Field PC11 PC10 Ñ
Reset
R/W
Addr
Figure 35-4. CPM Interrupt Pending/Mask/In-Service Registers (CIPR/CIMR/CISR)
In a vectored interrupt scheme, the CIPR clears the appropriate CIPR bit when the core
acknowledges the interrupt by setting CIVR[IACK]. The vector number corresponding to
the CPM interrupt source is then available for the core in CIVR[VN]. However, the CIPR
bit is not cleared if an event register exists for that interrupt source. Event registers exist
only for interrupt sources with multiple interrupt events (for example, the SCCs).
35-8
3 4 5 6
SCC3 SCC4 PC14 TIMER1 PC13
0000_0000_0000_0000
0x944 (CIPR), 0x948 (CIMR), 0x94C (CISR)
19 20 21 22
TIMER3 PC9 PC8 PC7
0000_0000_0000_0000
0x946 (CIPR), 0x94A (CIMR), 0x94E (CISR)
MPC860 PowerQUICC UserÕs Manual
Description
7 8 9 10
PC12 SDMA IDMA1 IDMA2
R/W
23 24 25 26
Ñ TIMER4 PC6 SPI
R/W
11 12 13 14
Ñ TIMER2 RTT
27 28 29 30
SMC1 SMC2 PC5 PC4
/PIP
MOTOROLA
15
I2C
31
Ñ