Motorola MPC860 PowerQUICC User Manual page 385

¥ RSV is low when the following is true:
Ñ AT0 = 0 (CPU access)
Ñ AT2 = 1 (Data)
Ñ AT3 = 0 (Reservation)
14.4.7.3.5 Burst Data in Progress (BDIP)
The master asserts BDIP to indicate to the slave that another data beat follows the current
data beat.
14.4.8 Termination Signals
The following sections discuss the termination signals supported by the MPC860.
14.4.8.1 Transfer Acknowledge (TA)
TA indicates normal completion of the bus transfer. The slave asserts TA with every data
beat returned or accepted during a burst cycle.
14.4.8.2 Burst Inhibit (BI)
The slave asserts BI to indicate to the master that it cannot burst. If this signal is asserted,
the master must transfer in multiple cycles and increment the address for the slave to
complete the burst transfer.
14.4.8.3 Transfer Error Acknowledge (TEA)
Terminates the bus cycle under a bus error condition for which the current cycle is aborted.
TEA overrides any other cycle termination signals, such as TA.
14.4.8.4 Termination Signals Protocol
The transfer protocol was deÞned to avoid electrical contention on lines that can be driven
by various sources. To do that, a slave should not drive signals associated with the data
transfer until the address phase is completed and it recognizes the address as its own. The
slave should disconnect from signals immediately after it has acknowledged the cycle and
no later than the termination of the next address phase cycle. This indicates that termination
signals should be connected to power through a pull-up resistor to prevent a master from
sampling undeÞned values in any of these signals when no real slave is addressed. See
Figure 14-25 and Figure 14-26.
MOTOROLA Chapter 14. MPC860 External Bus Interface
Part IV. Hardware Interface
14-33