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15.6 Clock and Power Control Registers
The following sections describe the clock and power control registers.
15.6.1 System Clock and Reset Control Register
The SPLL has a 32-bit control register that is powered by keep-alive power. The system
clock and reset control register (SCCR) is memory-mapped into the MPC860 SIUÕs register
map.
Bit
0
1
2
Field
Ñ
COM
HRESET
Ñ
#
POR
0
0
R/W
Addr
Bit
16
17
18
Field
Ñ
DFSYNC
HRESET
POR
R/W
Addr
Note: HRESET is hard reset and POR is power-on reset.
# The Þeld is undeÞned
ÑThe Þeld is unaffected.
* RTDIV depends on the combination of MODCK1 and MODCK2. RTSEL depends on MODCK1. See Table 15-4 for
more information.
This Þeld is set according to the default of the hard reset conÞguration word.
Bits
Name
0
Ñ
Reserved, should be cleared.
1Ð2
COM
Clock Output Module. This Þeld controls the output buffer strength of the CLKOUT pin. When both
bits are set, the CLKOUT pin is held in the high state. These bits can be dynamically changed
without generating spikes on the CLKOUT pin. If the CLKOUT pin is not connected to external
circuits, clock output should be disabled to minimize noise and power dissipation. The COM Þeld is
cleared by hard reset.
00 =Clock output enabled full-strength buffer.
01 =Clock output enabled half-strength output buffer.
10 =Reserved.
11 =Clock output disabled.
3Ð5
Ñ
Reserved, should be cleared.
MOTOROLA
3
4
5
6
7
Ñ
TBS RTDIV RTSEL CRQEN PRQEN
0
#
#
0
0
*
(IMMR&0XFFFF0000) + 280
19
20
21
22
23
DFBRG
DFNL
(IMMR&0XFFFF0000) + 282
Figure 15-15. SCCR
Table 15-8. SCCR Field Descriptions
Chapter 15. Clocks and Power Control
Part IV. Hardware Interface
8
9
10
#
0
0
*
0
0
R/W
24
25
26
DFNH
0
0
R/W
Description
11
12
13
14
15
Ñ
EBDF
Ñ
0
0
0
0
27
28
29
30
31
Ñ
15-27
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