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Part V. The Communications Processor Module
Table 21-8. SISTR Field Descriptions (Continued)
Bits
Name
2
CRORb
Address of the current route of TDMb receiverÑonly valid when SIGMR[RDM] = 11.
0 Address 128Ð191.
1 Address 192Ð255.
3
CROTb
Address of the current route of TDMb transmitterÑonly valid when SIGMR[RDM] = 11.
0 Address 384Ð447.
1 Address 448Ð511.
4Ð7 Ñ
Reserved, should be cleared.
21.2.4.6 SI RAM Pointer Register (SIRP)
The SI RAM pointer (SIRP) register, shown in Figure 21-23, indicates the RAM entry
currently being serviced. SIRP gives the real-time status location of the SI inside a TDM
frameÑuseful for debugging and synchronizing system activity with the TDMsÕ activity.
However, simply reading the status register SISTR is sufÞcient for most applications.
The user can determine which RAM entry in the SI RAM is in progress, but cannot
determine the status within that entry. For example, if the SIRP indicates an SI RAM entry
is active, but the entry is programmed to select four contiguous 8-bit time slots of a TDM,
it cannot be determined which of the four time slots is in progress. However, SIRP updates
the status as soon as the next SI RAM entry begins processing. The value of SIRP changes
on serial clock transitions. Before acting on the information in this register, perform two
reads to verify the same value is returned.
One of the four strobes can be connected externally to an interrupt pin to generate an
interrupt on a particular SI RAM entry to start or stop TSA execution.
The pointers in SIRP indicate the SI RAM entry word offset that is in progress.
Bit
0
1
Field
Ñ
VT
Reset
R/W
Addr
Bit
16
17
18
Field
Ñ
VR
Reset
R/W
Addr
Figure 21-23. SI RAM Pointer Register (SIRP)
21-26
2
3
4
5
6
TbPTR
19
20
21
22
RbPTR
MPC860 PowerQUICC UserÕs Manual
Description
7
8
9
10
11
Ñ
VTa
0
R
0XAF0
23
24
25
26
27
Ñ
VR
0
R
0xAF2
12
13
14
15
TaPTR
28
29
30
31
RaPTR
MOTOROLA
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