Instruction Flow - Motorola MPC860 PowerQUICC User Manual

Part II. PowerPC Microprocessor Module

4.3.1 Instruction Flow

As many as one instruction per clock cycle is fetched into the four-entry instruction queue
(IQ). The branch processing unit (BPU) predicts the outcome of branch instructions and in
some cases, resolves whether the branch is taken. Figure 4-2 shows general instruction
ßow.
Fetch (maximum one instruction per clock cycle)
Dispatch (maximum one instruction per clock cycle)
Retire (maximum one instruction per clock cycle)
Figure 4-2. Instruction Flow Conceptual Diagram
Nonbranch instructions reaching IQ0 are dispatched to the execution units at an optimal
rate of one instruction per clock cycle. An instruction cannot be dispatched unless it can
also take a position in the six-entry completion queue (CQ).
All branch instructions, including unconditional branch instructions, reaching IQ0 must
also take a position in the completion queue. This allows program order to be maintained,
it ensures a precise execution model, and it allows branch instructions to be used as
breakpoints.
All instructions enter the CQ along with processor state information that can be affected by
the instructionÕs execution. Executed arithmetic instructions pass their results both to
rename buffers and to the architected registers (typically GPRs), but to ensure program
order, instructions remain in the CQ until they can be retired.
If an exception occurs before the instruction can be retired, any results are removed from
the rename buffer and GPR and the instruction is ßushed from the completion queue, along
with subsequent instructions that have not executed or have not dispatched.
This information is used to enable out-of-order completion of instructions and ensure a
precise exception model. An instruction can be retired after all instructions ahead of it have
retired and it updates the architected destination registers without taking an exception.
4-6
Instruction Queue
Completion Queue
MPC860 PowerQUICC UserÕs Manual
IQ3
Branch
IQ2
IQ1
IQ0
CQ5
CQ4
CQ3
CQ2
CQ1
CQ0
Unit
Execution
Units
MOTOROLA