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27.9 Sending and Receiving the Synchronization
Sequence
The BISYNC channel can be programmed to send and receive a synchronization pattern
deÞned in the DSR. GSMR_H[SYNL] deÞnes pattern length, as shown in Table 27-7. The
receiver synchronizes on this pattern. Unless SYNL is zero (external sync), the transmitter
always sends the entire DSR contents, lsb Þrst, before each frameÑthe chosen 4- or 8-bit
pattern can be repeated in the lower-order bits.
Table 27-7. Receiver SYNC Pattern Lengths of the DSR
GSMR_H[SYNL]
Setting
00
01
10
11
27.10 Handling Errors in the SCC BISYNC
The controller reports message transmit and receive errors using the channel BDs, error
counters, and the SCCE. Modem lines can be directly monitored via the port C pins.
Table 27-8 describes transmit errors.
Error
Transmitter
The channel stops sending the buffer, closes it, sets TxBD[UN], and generates a TXE interrupt if it
Underrun
is enabled. The channel resumes transmission after a
Underrun cannot occur between frames or during a DLEÐ
CTS Lost during
The channel stops sending the buffer, closes it, sets TxBD[CT], and generates a TXE interrupt if
Message
not masked. Transmission resumes when a
Transmission
MOTOROLA
0
1
2
3
4
5
An external SYNC signal is used instead of the SYNC pattern in the DSR.
4-Bit
8-Bit
Transmit Errors
Table 27-8.
Chapter 27. SCC BISYNC Mode
Part V. The Communications Processor Module
Bit Assignments
6
7
8
9
10
11
16-Bit
Description
RESTART TRANSMIT
XXX
pair in transparent mode.
command is received.
RESTART TRANSMIT
12
13
14
15
command is received.
27-9
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