Motorola MPC860 PowerQUICC User Manual page 890

Part V. The Communications Processor Module
34.3 Port B
All port B signals can be open-drain. They are conÞgured independently as general-purpose
I/O signals if the corresponding bit in the PBPAR is cleared and they are conÞgured as
dedicated on-chip peripheral signals if the corresponding PBPAR bit is set. When
conÞgured as a general-purpose I/O signal, the signal direction of that signal is determined
by the corresponding control bit in the PBDIR. The port I/O signal is conÞgured as an input
if the corresponding PBDIR bit is cleared and it is conÞgured as an output if the
corresponding PBDIR bit is set. All PBPAR bits and PBDIR bits are cleared by hardware
reset, thus conÞguring all port B signals as general-purpose inputs. Table 34-6 describes
port B signal options. Port B is shared with the PIP, which is described in Chapter 33,
ÒParallel Interface Port.Ó
If a port B signal is selected as a general-purpose I/O signal, it can be accessed through the
PBDAT where data is stored in an output latch. If a port B signal is conÞgured as an output,
the output latch data is gated onto the port signal. When PBDAT is read, the port signal itself
is read.
All port B signals can have multiple conÞgurations, which include on-chip peripheral
2
functions for SPI, I C, SMCs, and the TDMs. Port B is also multiplexed with the PIP, which
can implement fast parallel interfaces. For a description of the dedicated PIP signal
functions, see Chapter 33, ÒParallel Interface Port.Ó
PB[26Ð28], and PB[15] are special in that their on-chip peripheral functions (BRGOx) are
also available in port A. This allows an alternate way to output BRG signals if other
functions are used. PB[16Ð19] are special in that their on-chip peripheral functions (RTSx
and L1STx) are available in port C providing an alternate location to output these signals if
other functions on port C are used. (The STBI and STBO signals (PB14 and PB15) used by
the PIP are not listed in Table 34-6. Section 33.7.1, ÒInterlocked Handshake Mode,Ó gives
instructions for enabling them
Signal
PBPAR[DDn] = 0
PB31 Port B31
PB30 Port B30
PB29 Port B29
PB28 Port B28
PB27 Port B27
PB26 Port B26
PB25 Port B25
34-8
.)
Table 34-6. Port B Pin Assignment
Signal Function
PBPAR[DDn] = 1
PBDIR[DRn] = 0 PBDIR[DRn] = 1
REJECT1
RSTRT2
Ñ SPIMOSI
BRGO4 SPIMISO
BRGO1
BRGO2
SMTXD1
MPC860 PowerQUICC UserÕs Manual
Input to On-chip Peripherals
SPISEL
SPICLK
SPIMISO = SPIMOSI
I2CSDA
I2CSCL
Ñ
(Default)
V
DD
SPICLK = GND
SPIMOSI = V
DD
I2CSDA = V
DD
I2CSCL = GND
Ñ
MOTOROLA