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30.4.1 SMC Transparent Mode Features
The following list summarizes the features of the SMC in transparent mode:
¥ Flexible buffers
¥ Can connect to a TDM bus using the TSA in the SI
¥ Can transmit and receive transparently on its own set of pins using a sync pin to
synchronize the beginning of transmission and reception to an external event
¥ Programmable character length (4Ð16)
¥ Reverse data mode
¥ Continuous transmission and reception modes
30.4.2 SMC Transparent-SpeciÞc Parameter RAM
There is no protocol-speciÞc parameter RAM for the SMC in transparent mode. Only the
general SMC parameter RAM is used. See Section 30.2.3, ÒSMC Parameter RAM.Ó
Table 30-11. SMC Transparent-Specific Parameter RAM Memory Map
Address
SMC base + 0x28
SMC base + 0x2A
SMC base + 0x2C
SMC base + 0x2E
SMC base + 0x30
Note: SMC base = IMMR + 0x3E80 (SMC1), 0x3F80 (SMC2).
30.4.3 SMC Transparent Channel Transmission Process
The transparent transmitter is designed to work with almost no core intervention. When the
core enables the SMC transmitter in transparent mode, it starts sending idles. The SMC
immediately polls the Þrst BD in the transmit channel BD table and once every character
time, depending on the character length (every 4 to 16 serial clocks). When there is a
message to transmit, the SMC fetches the data from memory and starts sending the message
when synchronization is achieved.
Synchronization can be achieved in two ways. First, when the transmitter is connected to a
TDM channel, it can be synchronized to a time slot. Once the frame sync is received, the
transmitter waits for the Þrst bit of its time slot before it starts transmitting. Data is sent only
during the time slots deÞned by the TSA. Secondly, when working with its own set of pins,
the transmitter starts sending when SMSYN
When a BD data is completely written to the transmit FIFO, the L bit is checked and if it is
set, the SMC writes the message status bits into the BD and clears the R bit. It then starts
transmitting idles. When the end of the current BD is reached and the L bit is not set, only
MOTOROLA
Name
Ñ
Ñ
Ñ
Ñ
Ñ
x
Chapter 30. Serial Management Controllers
Part V. The Communications Processor Module
Width
Description
Half word
Reserved
Half word
Reserved
Half word
Reserved
Half word
Reserved
Half word
Reserved
is asserted.
30-21
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