Motorola MPC860 PowerQUICC User Manual page 512

Part IV. Hardware Interface
17.4 Programming Model
This section describes the PCMCIA interface programming model. Generally, all registers
are memory-mapped within the internal control register area. The registers in Table 17-7
control the PCMCIA interface.
17.4.1 PCMCIA Interface Input Pins Register (PIPR)
Status of inputs from the PCMCIA card to the host (BVD, CD, RDY, VS) is reported to the
PIPR, shown in Figure 17-3. PIPR is a read-only register; write operations are ignored.
Bit 0 1
Field CAVS1 CAVS2 CAWP CACD2 CACD1 CABVD2 CABVD1 CARDY
Field
Reset
R/W
Addr
Bit 16 17
Field CBVS1 CBVS2 CBWP CBCD2 CBCD1 CBBVD2 CBBVD1 CBRDY
Reset
R/W
Addr
Figure 17-3. PCMCIA Interface Input Pins Register (PIPR)
Table 17-8 describes PIPR Þelds.
17-8
Table 17-7. PCMCIA Registers
Name
PIPR PCMCIA interface input pins register
PSCR PCMCIA interface status changed register
PER PCMCIA interface enable register
PGCRA PCMCIA interface general control register a
PGCRB PCMCIA interface general control register b
PBR[0Ð7] PCMCIA base registers 0Ð7 (per window)
POR[0Ð7] PCMCIA option registers 0Ð7 (per window)
2 3 4
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x0F0
18 19 20
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x0F2
Table 17-8. PIPR Field Descriptions
Bits Name
0 CAVS1 Voltage sense 1 for card A
1 CAVS2 Voltage sense 2 for card A
2 CAWP Write protect for card A
3 CACD2 Card detect 2 for card A
4 CACD1 Card detect 1 for card A
5 CABVD2 Battery voltage/SPKR IN for card A
MPC860 PowerQUICC UserÕs Manual
Description
5 6 7
Ñ
R
21 22 23
R
Description
8 9 10 11 12 13 14 15
Ñ
24 25 26 27 28 29 30 31
Ñ
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