Table of Contents
Advertisement
Paragraph
Number
14.4.5
Alignment and Data Packing on Transfers...................................................14-23
14.4.6
Arbitration Phase ..........................................................................................14-25
14.4.6.1
Bus Request..............................................................................................14-26
14.4.6.2
Bus Grant..................................................................................................14-26
14.4.6.3
Bus Busy...................................................................................................14-27
14.4.6.4
External Bus Parking................................................................................14-29
14.4.7
Address Transfer Phase-Related Signals......................................................14-29
14.4.7.1
Transfer Start ............................................................................................14-29
14.4.7.2
Address Bus..............................................................................................14-30
14.4.7.3
Transfer Attributes ...................................................................................14-30
14.4.7.3.1
14.4.7.3.2
14.4.7.3.3
14.4.7.3.4
14.4.7.3.5
14.4.8
Termination Signals......................................................................................14-33
14.4.8.1
Transfer Acknowledge (TA) ....................................................................14-33
14.4.8.2
Burst Inhibit (BI) ......................................................................................14-33
14.4.8.3
Transfer Error Acknowledge (TEA) ........................................................14-33
14.4.8.4
Termination Signals Protocol ...................................................................14-33
14.4.9
Memory Reservation ....................................................................................14-34
14.4.9.1
Cancel Reservation (CR)..........................................................................14-35
14.4.9.2
Kill Reservation (KR) ..............................................................................14-36
14.4.10
Bus Exception Control Cycles......................................................................14-37
14.4.10.1
RETRY.....................................................................................................14-38
15.1
Features...............................................................................................................15-1
15.2
The Clock Module ..............................................................................................15-3
15.2.1
External Reference Clocks .............................................................................15-3
15.2.1.1
Off-Chip Oscillator Input (EXTCLK)........................................................15-4
15.2.1.2
Crystal Oscillator Support (EXTAL and XTAL).......................................15-4
15.2.2
System PLL ....................................................................................................15-5
15.2.2.1
SPLL Reset Configuration .........................................................................15-6
15.2.2.2
SPLL Output Characteristics and Stability ................................................15-7
15.2.2.3
The System Phase-Locked Loop Pins (VDDSYN, VSSSYN,
15.2.2.4
Disabling the SPLL ....................................................................................15-9
15.3
Clock Signals......................................................................................................15-9
15.3.1
Clocks Derived from the SPLL Output ..........................................................15-9
xiv
CONTENTS
Read/Write ...........................................................................................14-30
Burst Indicator......................................................................................14-30
Transfer Size ........................................................................................14-30
Address Types ......................................................................................14-30
Burst Data in Progress (BDIP) .............................................................14-33
Chapter 15
Clocks and Power Control
VSSSYN1, XFC) ...................................................................................15-8
MPC860 PowerQUICC UserÕs Manual
Title
Page
Number
MOTOROLA
Advertisement
Table of Contents
