Motorola MPC860 PowerQUICC User Manual page 181

exception latency depends on the time required to reference memory. The measurement is
equal to the time taken for one of the following three events, in addition to the interval from
B to E as shown in Table 7-19.
¥ Longest load/store multiple/string instruction used
¥ or, one bus cycle for aligned access
¥ or, two bus cycles for unaligned access
System-level exception latency can be longer than the interval from B to E. If an instruction
ahead of the exception-causing instruction also generates an exception, that exception is
recognized Þrst. If it is important to minimize exception latency, exception handlers should
save the machine context and reenable exceptions as quickly as possible so pending
external exceptions are handled quickly.
Register settings for the external interrupt exception are shown in Table 7-6.
Table 7-6. Register Settings after an External Interrupt
Register
SRR0 Set to the effective address of the instruction that the processor would have attempted to execute next if
no interrupt conditions were present.
SRR1 0
1Ð4
5Ð9
10Ð15
16Ð31
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR POW 0
ILE Ñ
EE 0
PR 0
7.1.2.6 Alignment Exception (0x00600)
This section describes conditions that can cause alignment exceptions in the processor.
Similar to DSI exceptions, alignment exceptions use SRR0 and SRR1 to save the machine
state and DSISR to determine the source of the exception. An alignment exception occurs
when no higher priority exception exists and the implementation cannot perform a memory
access for one of the following reasons:
¥ The operand of lmw, stmw, lwarx, or stwcx. is not aligned.
¥ The instruction is lmw, stmw, lswi, lswx, stswi, or stswx and the processor is in
little-endian mode.
¥ An unaligned load or store in little-endian mode.
For lmw, stmw, lswi, lswx, stswi, and stswx instructions in little-endian mode, an
alignment exception always occurs. For lmw and stmw instructions with an operand that is
not aligned in big-endian mode, and for lwarx and stwcx. with an operand that is not
MOTOROLA
Setting Description
Loaded with equivalent bits from the MSR
Cleared
Loaded with equivalent bits from the MSR
Cleared
Loaded with equivalent bits from the MSR
FP 0
ME Ñ
SE 0
BE 0
Chapter 7. Exceptions
Part II. PowerPC Microprocessor Module
IP Ñ LE
IR 0
DR 0
RI 0
Set to value of ILE
7-7