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Table 22-6. SCCx Event, Mask, and Status Registers
Register &
IMMR Offset
SCCEx
SCC event register This 16-bit register reports events recognized by any of the SCCs. When an event
0xA10 (SCC1)
is recognized, the SCC sets its corresponding bit in SCCE, regardless of the corresponding mask bit.
0xA30 (SCC2)
When the corresponding event occurs, an interrupt is signaled to the CPIC. Bits are cleared by writing
0xA50 (SCC3)
ones (writing zeros has no effect). SCCE is cleared at reset and can be read at any time.
0xA70 (SCC4)
SCCMx
SCC mask register. The 16-bit, read/write register allows interrupts to be enabled or disabled using
0xA14 (SCC1)
the CPM for speciÞc events in each SCC channel. An interrupt is generated only if SCC interrupts in
0xA34 (SCC2)
this channel are enabled in the CPIC. If an SCCM bit is zero, the CPM does not proceed with interrupt
0xA54 (SCC3)
handling when that event occurs. If an SCCM bit is set, a 1 in the corresponding SCCE bit sets the
0xA74 (SCC4)
SCCx event bit in CIPR. The SCCM and SCCE bit positions are identical.
SCCSx
SCC status register. This 8-bit, read-only register allows monitoring of the real-time status of RXD. It
0xA17 (SCC1)
does not show the real-time status of CTS and CD, which is available in the parallel I/O data registers.
0xA37 (SCC2)
Interrupts caused by CTS and CD are described in Section 34.4, ÒPort C.Ó
0xA57 (SCC3)
0xA77 (SCC4)
Follow these steps to handle an SCC interrupt:
1. Once an interrupt occurs, read SCCE to determine the interrupt sources and clear
those SCCE bits (in most cases).
2. Process the TxBDs to reuse them if SCCE[TX] or SCCE[TXE] = 1. If the transmit
speed is fast or the interrupt delay is long, the SCC may have sent more than one Tx
buffer. Thus, it is important to check more than one TxBD during interrupt handling.
A common practice is to process all TxBDs in the handler until one is found with its
R bit set.
3. Extract data from the RxBD if SCCE[RX], SCCE[RXB], or SCCE[RXF] is set. As
with transmit buffers, if the receive speed is fast or the interrupt delay is long, the
SCC may have received more than one buffer and the handler should check more
than one RxBD. A common practice is to process all RxBDs in the interrupt handler
until one is found with its E bit set.
4. Clear CISR[SCCx].
5. Execute the rÞ instruction.
22.3.3 Initializing the SCCs
The SCCs require that a number of registers and parameters be conÞgured after a power-on
reset. Regardless of the protocol used, follow these steps to initialize SCCs:
1. Write the parallel I/O ports to conÞgure and connect the I/O pins to the SCCs.
2. Set the SDMA conÞguration register SDCR[RAID] Þeld to 0b01 (U-bus arbitration
priority level 5).
3. ConÞgure the parallel I/O registers to enable RTS, CTS, and CD if these signals are
required.
MOTOROLA
Chapter 22. Serial Communications Controllers
Part V. The Communications Processor Module
Description
22-17
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