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It closes the buffer when a stop or start condition is found on the I
error occurs. The core should write RxBD bits before the I
0
1
Offset + 0
E
Ñ
Offset + 2
Offset + 4
Offset + 6
Figure 32-13. I
Table 32-9 describes I
Bits Name
0
E
Empty.
0 The buffer is full or stopped receiving because of an error. The core can examine or write to any
Þelds of this RxBD, but the CPM does not use this BD while E = 0.
1 The buffer is empty or reception is in progress. The CPM owns this RxBD and its buffer. Once E is
set, the core should not write any Þelds of this RxBD.
1
Ñ
Reserved and should be cleared.
2
W
Wrap (last BD in table).
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CPM receives incoming data using the BD
pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the W
bit and overall space constraints of the dual-port RAM.
3
I
Interrupt.
0 No interrupt is generated after this buffer is full.
1 The I2CER[RXB] is set when the CPM Þlls this buffer, indicating that the core needs to process the
buffer. The RXB bit can cause an interrupt if it is enabled.
2
4
L
Last. The I
0 This buffer does not contain the last character of the message.
1 This buffer holds the last character of the message. The I
placed into the associated buffer, or because of a stop or start condition or an overrun.
5Ð13 Ñ
Reserved and should be cleared.
14
OV
Overrun. Set when a receiver overrun occurs during reception. The I
the received data is placed into the associated buffer.
15
Ñ
Reserved and should be cleared.
32.7.1.2 I
2
C Transmit Buffer Descriptor (TxBD)
Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The Þrst word
of the TxBD, shown in Figure 32-14, contains status and control bits.
MOTOROLA
2
3
4
5
W
I
L
2
C Receive Buffer Descriptor (RxBD)
2
C RxBD status and control bits.
2
Table 32-9. I
C RxBD Status and Control Bits
C controller sets L.
Chapter 32. I2C Controller
Part V. The Communications Processor Module
2
C controller is enabled.
6
7
8
9
10
Ñ
Data Length
RX Buffer Pointer
Description
2
C controller sets L after all received data is
2
C bus or when an overrun
11
12
13
14
OV
2
C controller updates this bit after
15
Ñ
32-13
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