Motorola MPC860 PowerQUICC User Manual page 819

However, to transmit three transparent 9-bit characters, the data length Þeld should be
initialized to 6 because the three 9-bit characters occupy three half words in memory.
The buffer pointer points to the Þrst byte of the buffer. They can be even or odd, unless
character length is greater than 8 bits, in which case the transmit buffer pointer must be
even. For instance, the pointer to 8-bit transparent characters can be even or odd, but the
pointer to 9-bit transparent characters must be even. The buffer can reside in internal or
external memory.
30.4.11 SMC Transparent Event Register (SMCE)/Mask Register
(SMCM)
The SMC event register (SMCE) generates interrupts and reports events recognized by the
SMC channel. When an event is recognized, the SMC sets the corresponding SMCE bit.
Interrupts are masked in the SMCM, which has the same format as the SMCE. SMCE bits
are cleared by writing ones; writing zeros has no effect. Unmasked bits must be cleared
before the CP clears the internal interrupt request.
Figure 30-15 shows the SMCE/SMCM register format.
Bit 0
Field
Reset
R/W
Address
Figure 30-15. SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
Table 30-17 describes SMCE/SMCM Þelds.
Bits Name
0Ð2 Ñ Reserved, should be cleared.
3 TXE Tx error. Set when an underrun error occurs on the transmitter channel.
4 Ñ Reserved, should be cleared.
5 BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Reception
begins after a new buffer is provided, without waiting for resynchronization. To resynchronize after error
recovery, issue an
6 TX Tx buffer. Set after a buffer is sent. If the L bit of the TxBD is set, TX is set when the last character
starts being sent. A one character-time delay is required to ensure that data is completely sent over the
transmit pin. If the L bit of the TxBD is cleared, TX is set when the last character is written to the
transmit FIFO. A two character-time delay is required to ensure that data is completely sent.
7 RX Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and its
associated RxBD is closed.
MOTOROLA
1 2
Ñ
0xA86 (SMCE1), 0xA96 (SMCE2)/ 0xA8A (SMCM1), 0xA9A (SMCM2)
Table 30-17. SMCE/SMCM Field Descriptions
command.
ENTER HUNT MODE
Chapter 30. Serial Management Controllers
Part V. The Communications Processor Module
3 4
TXE Ñ BSY
0
R/W
Description
5 6 7
TX RX
30-29