Motorola MPC860 PowerQUICC User Manual page 179

7.1.2.1 System Reset Interrupt (0x00100)
A system reset interrupt occurs when IRQ0 is asserted. When the exception is taken,
processing begins at offset 0x00100. A hard or soft reset also causes program execution to
begin fetching at 0x00100 after the associated reset actions. Table 7-4 shows register
settings.
Table 7-4. Register Settings after a System Reset Interrupt Exception
Register
SRR0 Set to the EA of the next instruction of the interrupted process.
SRR1 Saves the machine status prior to exceptions and to restore status when an rÞ instruction is executed.
1Ð4 0
10Ð15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Value of MSR[ILE] of the interrupted process.
Others 0
7.1.2.2 Machine Check Interrupt (0x00200)
A machine check interrupt indication is received from the U bus in response to an address
or data tenure. It is typically caused by an access for which the address does not exist or a
data error occurs.
As deÞned in the OEA, machine check interrupts are enabled when MSR[ME] = 1. If
MSR[ME] = 0 and a machine check condition is detected, the processor enters the
checkstop state. The behavior of the core in checkstop state is dependent on the working
mode as deÞned in Section 37.3.1.1, ÒDebug Mode Enable vs. Debug Mode Disable.Ó
When debug mode is enabled, debug mode is entered instead of checkstop state. When
debug mode is disabled, instruction processing is suspended and cannot be restarted
without resetting the core.
An indication that can generate an automatic reset in this condition is sent to the system
interface unit. See Chapter 11, ÒSystem Interface Unit,Ó for more details. If MSR[ME] = 1,
the machine check interrupt is taken. If SRR1[30] = 1, the interrupt is recoverable.
Instruction fetching begins at offset 0x00200 and the registers are set as shown in Table 7-5.
MOTOROLA
Part II. PowerPC Microprocessor Module
Setting
Chapter 7. Exceptions 7-5