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FFY — Feed Forward Y Operand
This control bit is used to force the content of the WBBR to be used as the Y operand
value of the first instruction to be executed following an update of the CPUSCR. This
gives the debug firmware the capability of updating processor registers by initializing
the WBBR with the desired value, setting the FFY bit, and executing a mov instruc-
tion to the desired register.
FDB — Force PSR Debug Enable Mode
Setting this control bit places the processor in debug enable mode. In debug enable
mode, execution of the bkpt instruction as well as recognition of the BRKRQ input
causes the processor to enter debug mode, as if the DBGRQ input had been
asserted.
SZ — Prefetch Size
This control field is used to drive the CPU SIZ[1:0] outputs on the first instruction
prefetch caused by issuing a OnCE command with the GO bit set and not ignored. It
should be set to indicate a 16-bit size, i.e., 0b10. This field should be restored to its
original value after a debug session is completed, i.e., when a OnCE command is
issued with the GO and EX bits set and not ignored.
TC — Prefetch Transfer Code
This control field is used to drive the CPU TC[2:0] outputs on the first instruction
prefetch caused by issuing a OnCE command with the GO bit set and not ignored. It
should typically be set to indicate a supervisor instruction access, i.e., 0b110. This
field should be restored to its original value after a debug session is completed, i.e.,
when a OnCE command is issued with the GO and EX bits set and not ignored.
16.11.4 Write-Back Bus Register (WBBR)
The write-back bus register (WBBR) is used as a means of passing operand informa-
tion between the CPU and the external command controller. Whenever the external
command controller needs to read the contents of a register or memory location, it
forces the device to execute an instruction that brings that information to WBBR.
For example, to read the content of processor register r0, a mov r0,r0 instruction is
executed, and the result value of the instruction is latched into the WBBR. The con-
tents of WBBR can then be delivered serially to the external command controller.
To update a processor resource, this register is initialized with a data value to be writ-
ten, and a mov instruction is executed which uses this value as a write-back data
value. The FFY bit in the control state register forces the value of the WBBR to be
substituted for the normal source value of a mov instruction, thus allowing updates to
processor registers to be performed.
16.11.5 Processor Status Register (PSR)
The OnCE processor status register (PSR) is a 32-bit latch used to read or write the
M•CORE processor status register. Whenever the external command controller
needs to save or modify the contents of the M•CORE processor status register, this
register is used. This register is affected by the operations performed in debug mode
and must be restored by the external command controller when returning to normal
mode.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
OnCE™ DEBUG MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
16-19
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