Figure 6-21: Single Color 8-Bit Panel Timing (Format 1) - Epson S1D13706 Technical Manual

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6.4.5 Single Color 8-Bit Panel Timing (Format 1)

- The duty cycle of FPSHIFT changes in order to process 16 pixels in 6 FPSHIFT/FPSHIFT2 rising edges

- Ts = Pixel clock period (PCLK)

- Diagram drawn with 2 FPLINE vertical blank period

- Example timing for a 320x240 panel

= Vertical Display Period

= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines

= Vertical Non-Display Period

= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines

= Horizontal Display Period

= ((REG[14h] bits 6-0) + 1) x 8Ts

= Horizontal Non-Display Period

= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)

X31B-A-001-08

Figure 6-21: Single Color 8-Bit Panel Timing (Format 1)

Epson Research and Development

Vancouver Design Center

Hardware Functional Specification

Issue Date: 01/11/13

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