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EPSON
F00A
Pin Name
Type
Pin No.
VD0–VD15
I/O
44–51,
54–61
VA0–VA15
O
33–43,
62–66
VCS1#
O
69
VCS0#
O
68
VWE#
O
67
VOE#
O
83
TM
FPDI-1
Pin Name
#1
Pin Name
UD3–UD0
UD3–UD0
LD3–LD0
LD3–LD0
XSCL
FPSHIFT
LP
FPLINE
WF/
MOD
XSCL2
FPSHIFT2
YD
FPFRAME
LCDENB
#1 VESA Flat Panel Display Interface Standard (FPDI-1
F00A
Pin Name
Type
Pin No.
OSC1
I
92
OSC2
O
93
F00A
Pin Name
Type
Pin No.
V
P
3, 53
DD
V
P
2, 52
SS
1-14
Table 5-2 Display Memory Interface
F01A
D00A
Driver
Pin No.
Pad No.
41–48,
54–55,
TS1D2 These pins are connected to the display memory data bus. For 16-bit
51–58
57–61,
64,
68–75
30–40,
38–40,
CO1
59–63
42–43,
45–46,
48–49,
51–52,
77–81
66
84
CO1
65
83
CO1
64
82
CO1
80
102
CO1
Table 5-3 LCD Interface
F00A
F01A
Type
Pin No.
Pin No.
Pad No.
O
70–73,
67–70,
74–77
71–74
O
81
78
O
79
76
O
80
77
O
78
75
O
82
79
Table 5-4 Clock Inputs
F01A
D00A
Driver
Pin No.
Pad No.
∗
92
115
∗
93
116
Table 5-5 Power Supply
F01A
D00A
Driver
Pin No.
Pad No.
50, 100
3, 67
P
49, 99
1, 65
P
interface, VD0–VD7 are connected to the display memory data bus
of even byte addresses and VD8–VD15 are connected to the display
memory data bus of odd byte addresses. The output drivers of these
pins are placed in a high impedance state when RESET is high.
On the falling edge of RESET, the values of VD0–VD15 are latched
into the chip to configure various hardware options (see Table 5-6 on
page 15).
These pins are connected to the display memory address bus.
Active low chip-select output to the second or odd byte address
SRAM. See Display Memory Interface section for details.
Active low chip-select output to the first or even byte address
SRAM. See Display Memory Interface section for details.
Active low output used for writing data to the display memory. This
pin is connected to the WE# input of the SRAMs.
Active low output to enable reading of data from the display mem-
ory. This pin is connected to the OE# input of the SRAMs.
D00A
Driver
86–89,
CO3S Panel display data bus. The data format depends on the
90–93
specific panel connected. For 4-bit single panels,
LD3–LD0 are driven low (0 state).
100
CO3
Display data shift clock. Data is shifted into the LCD
X-drivers on the falling edge of this signal.
96
CO3
Display data latch clock. The falling edge of this sig-
nal is used to latch a row of display data in the LCD
X-drivers and to turn on the Y driver (row driver).
97
CO3
For format 1 of 8-bit single color panels this is the sec-
ond shift clock.
For all other modes, this is the LCD backplane BIAS
signal. This output toggles once every frame, or as
programmed in AUX[05] bits 7–2.
94
CO3
Vertical scanning start pulse. A logic '1' on this signal,
sampled by the LCD module on the falling edge of LP,
is used by the panel Y driver (row driver) to indicate
the start of the vertical frame.
101
CO2
LCD enable signal output. It can be used externally to
turn off the panel supply voltage and backlight.
TM
)
This pin, along with OSC2, is the 2-terminal crystal interface when
using a 2-terminal crystal as the clock input. If an external oscillator
is used as a clock source, then this pin is the clock input.
This pin, along with OSC1, is the 2-terminal crystal interface when
using a 2-terminal crystal as the clock input. If an external oscillator
is used as a clock source this pin should be left unconnected.
Voltage supply.
Voltage ground.
Description
Description
Description
Description
S18A-A-011-01
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