Lcd Interface Pin Mapping; Table 5-3: Lcd Interface Pin Mapping - Epson S1D13704 Technical Manual

Epson Research and Development
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5.5 LCD Interface Pin Mapping

Monochrome Passive Panel
S1D13704
4-bit
Pin Name
Single
FPFRAME
FPLINE
FPSHIFT
DRDY MOD
FPDAT0 driven 0
FPDAT1 driven 0
FPDAT2 driven 0
FPDAT3 driven 0
FPDAT4 D0
FPDAT5 D1
FPDAT6 D2
FPDAT7 D3
FPDAT8 GPIO1
FPDAT9 GPIO2
FPDAT10 GPIO3
GPIO4/
FPDAT11 HW Video
Invert
Note
Hardware Functional Specification
Issue Date: 01/02/08

Table 5-3: LCD Interface Pin Mapping

8-bit
8-bit Dual
Single
MOD MOD
D0 LD0 driven 0
D1 LD1 driven 0
D2 LD2 driven 0
D3 LD3 driven 0
D4 UD0
D5 UD1
D6 UD2
D7 UD3
GPIO1 GPIO1
GPIO2 GPIO2
GPIO3 GPIO3
GPIO4/ GPIO4/ GPIO4/
HW Video HW Video HW Video
Invert Invert
1. Unused GPIO pins must be connected to IO V
2. Hardware Video Invert is enabled on FPDAT11 by REG[02h] bit 1.
Color Passive Panel
8-bit 8-bit
4-bit
Single Single
Single
Format 1 Format 2
FPFRAME
FPLINE
FPSHIFT
MOD FPSHIFT2 MOD
D0
D1
D2
D3
D0 D4
D1 D5
D2 D6
D3 D7
GPIO1 GPIO1 GPIO1
GPIO2 GPIO2 GPIO2
GPIO3 GPIO3 GPIO3
GPIO4/ GPIO4/
*
HW Video HW Video
Invert Invert Invert
Color TFT/D-TFD
8-bit Dual 9-bit
MOD
D0 LD0 R2
D1 LD1 R1
D2 LD2 R0
D3 LD3 G2
D4 UD0 G1
D5 UD1 G0
D6 UD2 B2
D7 UD3 B1
GPIO1 B0
GPIO2 GPIO2
GPIO3 GPIO3
GPIO4/
HW Video GPIO4
Invert
.
DD
Page 23
12-bit
DRDY
R3
R2
R1
G3
G2
G1
B3
B2
B1
R0
G0
B0
S1D13704
X26A-A-001-04