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Page 24
Pin
F00A
Type
Name
Pin #
VD0-
44 - 51,
I/O
VD15
54 - 61
VA0-
33 - 43,
O
VA15
62 - 66
VCS1# O
69
VCS0# O
68
VWE# O
67
VOE#
O
83
S1D13503
X18A-A-001-08
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Table 5-2: Display Memory Interface
F01A
D00A
Driver
Description
Pin #
Pad #
These pins are connected to the display memory data bus. For 16-
bit interface, VD0-VD7 are connected to the display memory data
bus of even byte addresses and VD8-VD15 are connected to the
display memory data bus of odd byte addresses. The output drivers
54-55,
of these pins are placed in a high impedance state when RESET is
41 - 48,
57-61,
high.
TS1D2
51 - 58
64,
On the falling edge of RESET, the values of VD0-VD15 are
68-75
latched into the chip to configure various hardware options (see
Section Table 5-6: on page 26).
VD0-VD15 each have an internal pull-down resistor (see Section
Table 6-3: on page 27).
38-40,
42-43,
30 - 40
45-46,
CO1
These pins are connected to the display memory address bus.
59 - 63
48-49,
51-52,
77-81
Active low chip-select output to the second or odd byte address
66
84
CO1
SRAM. See Display Memory Interface section for details.
Active low chip-select output to the first or even byte address
65
83
CO1
SRAM. See Display Memory Interface section for details.
Active low output used for writing data to the display memory.
64
82
CO1
This pin is connected to the WE# input of the SRAMs.
Active low output to enable reading of data from the display
80
102
CO1
memory. This pin is connected to the OE# input of the SRAMs.
Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 01/01/29
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