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3 Typical System Implementation Diagrams
SH-4
BUS
CSn#
A[15:0]
D[15:0]
WE1#
BS#
RD/WR#
RD#
WE0#
RDY#
CKIO
RESET#
SH-3
BUS
CSn#
A[15:0]
D[15:0]
WE1#
BS#
RD/WR#
RD#
WE0#
WAIT#
CKIO
RESET#
S1D13704
X26A-A-001-04
CS#
AB[15:0]
DB[15:0]
WE1#
S1D13704
BS#
RD/WR#
RD#
WE0#
WAIT#
BCLK
RESET#
Figure 3-1: Typical System Diagram (SH-4 Bus)
CS#
AB[15:0]
DB[15:0]
WE1#
S1D13704
BS#
RD/WR#
RD#
WE0#
WAIT#
BCLK
RESET#
Figure 3-2: Typical System Diagram (SH-3 Bus)
.
Oscillator
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
.
*
Oscillator
FPDAT[3:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
Epson Research and Development
Vancouver Design Center
D[7:0]
FPSHIFT
8-bit
FPFRAME
LCD
FPLINE
Display
MOD
D[3:0]
FPSHIFT
4-bit
FPFRAME
LCD
FPLINE
Display
MOD
Hardware Functional Specification
Issue Date: 01/02/08