Dual Color 16-Bit Panel Timing; Figure 7-35: Dual Color 16-Bit Panel Timing; Vancouver Design Center - Epson S1D13504 Technical Manual

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7.4.11 Dual Color 16-Bit Panel Timing

FPFRAME
FPLINE
MOD
UD[7:0], LD[7:0]
FPLINE
MOD
FPSHIFT
UD7, LD7
UD6, LD6
UD5, LD5
UD4, LD4
UD3, LD3
UD2, LD2
UD1, LD1
UD0, LD0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 01/01/30
VDP
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244
HDP
1-R1, 1-B3,
241-B 3
241-R1
1-G1, 1-R4,
241-G1 241-R4
1-B1, 1-G4,
241-B 1 241-G 4
1-R2, 1-B4,
241-R2 241-B 4
1-G2, 1-R5,
241-G2 241-R5
1-B2, 1-G5,
241-G 5
241-B 2
1-R3, 1-B5,
241-R3 241-B5
1-G3, 1-R6,
241-G3 241-R6

Figure 7-35: Dual Color 16-Bit Panel Timing

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
VNDP
LINE 239/479 LINE 240/480
1-G638,
241-G638
1-B638,
241-B638
1-R639,
241-R639
1-G639,
241-G63 9
1-B639,
241-B639
1-R640,
241-R640
1-G 640,
241-G640
1-B640,
241-B640
Page 81
LINE 1/241 LINE 2/242
HNDP
S1D13504
X19A-A-002-18