16-Bit Dual Color Passive Lcd Panel Timing - Epson S1D13505F00A Technical Manual

16-Bit Dual Color Passive LCD Panel Timing

FPFRAME
FPLINE
MOD
UD[7:0], LD[7:0]
FPLINE
MOD
FPSHIFT
UD7, LD7
UD6, LD6
UD5, LD5
UD4, LD4
UD3, LD3
UD2, LD2
UD1, LD1
UD0, LD0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-40 16-Bit Dual Color Passive LCD Panel Timing
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)*8Ts
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
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VDP
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480
HDP
1-R1, 1-B3,
241-R 1 2 41-B 3
1-G1,
1-R 4 ,
24 1-G 1
2 41 -R 4
1-B1, 1-G 4,
2 4 1-B 1 2 41-G 4
1-R2, 1-B4,
2 41 -R 2 2 41-B 4
1-G2, 1-R 5 ,
24 1-G 2 2 41 -R 5
1-B2, 1-G 5,
2 4 1-B 2 2 41-G 5
1-R3, 1-B5,
2 41 -R 3
2 41-B5
1-G3, 1-R 6 ,
24 1-G 3
2 41 -R 6
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
EPSON
7: A.C. CHARACTERISTICS
VNDP
LINE 1/241 LINE 2/242
HNDP
1-G 63 8,
2 41 -G 6 3 8
1-B63 8,
24 1-B638
1-R 639 ,
24 1 -R 639
1-G 63 9,
2 41 -G 6 3 9
1 -B63 9,
2 4 1-B6 3 9
1-R 640 ,
24 1 -R6 40
1-G 6 40,
2 4 1-G 64 0
1 -B64 0,
2 4 1-B6 4 0
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