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ZiLOG Z8018 Series User Manual

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Z8018x
Family MPU
User Manual
UM005004-0918
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Sam Sawyer
January 25, 2025

are there a timing diagrams for PUSH and POP instructions?

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Summary of Contents for ZiLOG Z8018 Series

  • Page 1 Z8018x Family MPU User Manual UM005004-0918 www.zilog.com...
  • Page 2 Windows is a registered trademark of Microsoft Corporation. Document Disclaimer © 2018 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC.
  • Page 3 Z80180/Z8S180/ Z8L180. These cores and base peripheral sets are used in a large family of ZiLOG products. Below is a list of ZiLOG products that use this class of processor, along with the associated processor family. This document is...
  • Page 4 Presents the AC parameters for the Z8018x MPUs. Timing Diagrams Contains timing diagrams and standard test conditions for the Z8018x MPUs. Appendices The appendixes in this manual provide additional information applicable to the Z8018x family of ZiLOG MPUs: • Instruction set • Instruction summary table •...

  • Page 5: Table Of Contents

    Z8018x Family MPU User Manual Table of Contents Z80180, Z8S180, Z8L180 MPU Operation ....1 Features ...........1 General Description .
  • Page 6 Z8018x Family MPU User Manual Baud Rate Generator (Z8S180/Z8L180-Class Processors Only) ....143 Clocked Serial I/O Port (CSI/O) ......146 CSI/O Registers Description .
  • Page 7 Z8018x Family MPU User Manual Flag ........... .209 Miscellaneous .
  • Page 8 Z8018x Family MPU User Manual viii List of Figures Z80180, Z8S180, Z8L180 MPU Operation ....1 Figure 1. 64-Pin DIP ........3 Figure 2.
  • Page 9 Z8018x Family MPU User Manual Figure 21. SLEEP Timing Diagram ......35 Figure 22. I/O Address Relocation ......43 Figure 23.
  • Page 10 Z8018x Family MPU User Manual Figure 49. TEND0 Output Timing Diagram ....108 Figure 50. DMA Interrupt Request Generation ....114 Figure 51.
  • Page 11 Z8018x Family MPU User Manual Software Architecture ........173 Figure 74.
  • Page 12 Z8018x Family MPU User Manual List of Tables Z80180, Z8S180, Z8L180 MPU Operation ....1 Table 1. Status Summary ....... . .10 Table 2.
  • Page 13 Z8018x Family MPU User Manual xiii Table 23. Timer Output Control ......163 Table 24. E Clock Timing in Each Condition .
  • Page 14 Z8018x Family MPU User Manual Table 43. Block Transfer ....... . . 225 Table 44.

  • Page 15: Z80180, Z8S180, Z8L180 Mpu Operation

    • On-Chip Clock Oscillator/Generator • Clocked Serial I/O Port • Code Compatible with ZiLOG Z80 CPU • Extended Instructions GENERAL DESCRIPTION Based on a microcoded execution unit and an advanced CMOS manufacturing technology, the Z80180, Z8S180, Z8L180 (Z8X180) is an...
  • Page 16 Z8018x Family MPU User Manual on-chip memory management unit (MMU) with the capability of addressing up to 1 MB of memory. Reduced system costs are obtained by incorporating several key system functions on-chip with the CPU. These key functions include I/O devices such as DMA, UART, and timer channels.

  • Page 17: Figure 1. 64-Pin Dip

    Z8018x Family MPU User Manual XTAL EXTAL WAIT BUSACK BUSREQ MREQ RESET IORQ RFSH INT0 HALT INT1 TEND1 INT2 DREQ1 RXS/CTS1 CKA1/TEND0 Z8X180 RXA1 TXA1 CKA0/DREQ0 RXA0 TXA0 DCO0 CTS0 RTS0 A18/TOUT Figure 1. 64-Pin DIP UM005004-0918...

  • Page 18: Figure 2. 68-Pin Plcc

    Z8018x Family MPU User Manual INT0 HALT INT1 TEND1 INT2 DREQ1 RXS/CTS1 CKA1/TEND0 RXA1 Z8X180 TEST TXA1 CKA0/DREQ0 RXA0 TXA0 DCD0 CTS0 RTS0 Figure 2. 68-Pin PLCC UM005004-0918...

  • Page 19: Figure 3. 80-Pin Qfp

    Z8018x Family MPU User Manual RFSH INT0 HALT INT1 TEND1 INT2 DREQ1 RXS/CTS1 Z8X180 CKA1/TEND0 RXA1 TEST TXA1 CKA0/DREQ0 RXA0 TXA0 DCD0 RTS0 Figure 3. 80-Pin QFP UM005004-0918...

  • Page 20: Figure 4. Z80180/Z8S180/Z8L180 Block Diagram

    Z8018x Family MPU User Manual Interrupt Bus State Control Timing Generator DREQ1 16-bit TEND1 Programmable DMACs A18/TOUT Reload Timers TXA0 Clocked CKA0/DREQ0 Serial I/O RXS/CTS1 Port Asynchronous RXA0 (Channel 0) RTS0 CTS0 DCD0 TXA1 Asynchronous CKA1/TEND0 (channel 1) RXA1 Data Address Buffer Buffer...

  • Page 21: Pin Description

    Z8018x Family MPU User Manual PIN DESCRIPTION A0–A19. Address Bus (Output, Active High, 3-state). A0–A19 form a 20- bit address bus. The Address Bus provides the address for memory data bus exchanges, up to 1 MB, and I/O data bus exchanges, up to 64K. The address bus enters a high impedance state during RESET and external bus acknowledge cycles.
  • Page 22 Z8018x Family MPU User Manual D0–D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute an 8-bit bidirectional data bus, used for the transfer of information to and from I/O and memory devices. The data bus enters the high impedance state during RESET and external bus acknowledge cycles. DCD0.
  • Page 23 Z8018x Family MPU User Manual BUSREQ, and INT0 signals are inactive. The CPU acknowledges these interrupt requests with an interrupt acknowledge cycle. Unlike the acknowledgment for INT0, during this cycle neither the M1 or IORQ signals become Active. IORQ. I/O Request (Output, Active Low, 3-state). IORQ indicates that the address bus contains a valid I/O address for an I/O read or I/O write operation.

  • Page 24: Table 1. Status Summary

    Z8018x Family MPU User Manual RTS0. Request to Send 0 (Output, Active Low). This output is a programmable modem control signal for ASCI channel 0. RXA0, RXA1. Receive Data 0 and 1 (Inputs, Active High). These signals are the receive data to the ASCI channels. RXS.
  • Page 25 Z8018x Family MPU User Manual TOUT. Timer Out (Output, Active High). TOUT is the pulse output from PRT channel 1. This line is multiplexed with A18 of the address bus. TXA0, TXA1. Transmit Data 0 and 1 (Outputs, Active High). These signals are the transmitted data from the ASCI channels.

  • Page 26: Architecture

    Z8018x Family MPU User Manual Table 2. Multiplexed Pin Descriptions Multiplexed Pins Descriptions During RESET, this pin is initialized as A18 pin. If either TOC1 or TOC0 bit of the Timer Control Register (TCR) is set A18/TOUT to 1, TOUT function is selected. If TOC1 and TOC0 bits are cleared to 0, A18 function is selected.
  • Page 27 Z8018x Family MPU User Manual • Programmable Reload Timers (PRT, 2 channels) • Clock Serial I/O (CSIO) channel. Other Z8X180 family members (such as Z80183, Z80S183, Z80185/195) feature, in addition to these blocks, additional peripherals and are covered in their associated Product Specification Clock Generator This logic generates the system clock from either an external crystal or clock input.
  • Page 28 Z8018x Family MPU User Manual Central Processing Unit The CPU is microcoded to provide a core that is object code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply and divide. This core has been enhanced to allow many of the instructions to execute in fewer clock cycles.

  • Page 29: Operation Modes

    Z8018x Family MPU User Manual OPERATION MODES The Z8X180 can be configured to operate like the Hitachi HD64180. This functionality is accomplished by allowing user control over the M1, IORQ, WR, and RD signals. The Operation Mode Control Register (OMCR), illustrated in Figure 5, determines the M1 options, the timing of the IORQ, RD, and WR signals, and the RETI operation.

  • Page 30: Figure 6. M1 Temporary Enable Timing

    Z8018x Family MPU User Manual Op Code Fetch Write into OMCR Figure 6. M1 Temporary Enable Timing M1TE (M1 Temporary Enable): This bit controls the temporary assertion of the M1 signal. It is always read back as a 1 and is set to 1 during RESET.

  • Page 31: Figure 7. I/O Read And Write Cycles With Ioc

    Z8018x Family MPU User Manual IORQ Figure 7. I/O Read and Write Cycles with IOC = 1 Timing Diagram When IOC is , the timing of the IORQ and RD signals match the timing required by the Z80 family of peripherals. The IORQ and RD signals go active as a result of the rising edge of T2.

  • Page 32: Cpu Timing

    Z8018x Family MPU User Manual The user must program the Operation Mode Control Register Note: before the first I/O instruction is executed. CPU Timing This section explains the Z8X180 CPU timing for the following operations: • Instruction (Op Code) fetch timing •...

  • Page 33: Figure 9. Op Code Fetch (Without Wait State) Timing Diagram

    Z8018x Family MPU User Manual The Op Code on the data bus is latched at the rising edge of T3 and the bus cycle terminates at the end of T3. – – WAIT MREQ Figure 9. Op Code Fetch (without Wait State) Timing Diagram Figure 10 illustrates the insertion of Wait States (TW) into the Op Code fetch cycle.

  • Page 34: Figure 10. Op Code Fetch (With Wait State) Timing Diagram

    Z8018x Family MPU User Manual – – Op Code WAIT MREQ Figure 10. Op Code Fetch (with Wait State) Timing Diagram Operand and Data Read/Write Timing The instruction operand and data read/write timing differs from Op Code fetch timing in two ways: •...
  • Page 35 Z8018x Family MPU User Manual Wait States (TW) are inserted as previously described for Op Code fetch cycles. Figure 11 illustrates the read/write timing without Wait States (Tw), while Figure 12 illustrates read/write timing with Wait States (TW). Read Cycle Write Cycle –...
  • Page 36 Z8018x Family MPU User Manual Read Cycle Write Cycle – – Read data Write data WAIT MREQ Figure 12. Memory Read/Write (with Wait State) Timing Diagram I/O Read/Write Timing I/O Read/Write operations differ from memory Read/Write operations in the following three ways: •...

  • Page 37: Figure 13. I/O Read/Write Timing Diagram

    Z8018x Family MPU User Manual I/O Read Cycle I/O Write Cycle – I/O address I/O address – Read data Write data WAIT IORQ Figure 13. I/O Read/Write Timing Diagram Basic Instruction Timing An instruction may consist of a number of machine cycles including Op Code fetch, operand fetch, and data read/write cycles.

  • Page 38: Figure 14. Instruction Timing Diagram

    Z8018x Family MPU User Manual CPU internal Displacement 1st Op Code 2nd Op Code Next instruction Memory Operation Read Cycle Fetch Cycle Fetch Cycle Fetch Cycle Write Cycle T1 T2 T3 T1 T3 T1 T2 T3 T1 T1 T1 T1 T2 T3 –...

  • Page 39: Figure 15. Reset Timing Diagram

    Z8018x Family MPU User Manual The external bus is IDLE while the CPU computes the effective address. Finally, the computed memory location is written with the contents of the CPU register (g). RESET Timing Figure 15 depicts the Z8X180 hardware RESET timing. If the RESET pin is Low for six or more clock cycles, processing is terminated and the Z8X180 restarts execution from (logical and physical) address 00000H...

  • Page 40: Figure 16. Bus Exchange Timing During Memory Read

    Z8018x Family MPU User Manual When the bus is released, the address (A0–A19), data (D0–D7), and control (MREQ, IORQ, RD, and WR) signals are placed in the high impedance state. Dynamic RAM refresh is not performed when the Z8X180 has released the bus.

  • Page 41: Wait State Generator

    Z8018x Family MPU User Manual CPU Internal Operation Bus Release Cycle CPU Cycle – – MREQ IORQ RD, WR BUSREQ BUSACK Figure 17. Bus Exchange Timing During CPU Internal Operation Wait State Generator To ease interfacing with slow memory and I/O devices, the Z8X180 uses Wait States (TW) to extend bus cycle timing.

  • Page 42: Figure 18. Wait Timing Diagram

    Z8018x Family MPU User Manual externally synchronizing WAIT input transitions with the rising edge of the system clock. Dynamic RAM refresh is not performed during Wait States (TW) and thus system designs which use the automatic refresh function must consider the affects of the occurrence and duration of wait states (TW).

  • Page 43: Figure 19. Memory And I/O Wait State Insertion (Dcntl - Dma/Wait Control Register)

    Z8018x Family MPU User Manual MWI1 MWI0 MWI1 MWI0 Figure 19. Memory and I/O Wait State Insertion (DCNTL – DMA/Wait Control Register) The number of Wait States (TW) inserted in a specific cycle is the maximum of the number requested by the WAIT input, and the number automatically generated by the on-chip Wait State generator.

  • Page 44: Table 4. Wait State Insertion

    Z8018x Family MPU User Manual inserted depending on the programmed value in IWI1 and IWI0. Refer to Table 4. Table 4. Wait State Insertion The Number of Wait States For INT1, For NMI INT2 and interrupt For INT0 internal acknowledge For internal interrupt interrupts...

  • Page 45: Halt And Low Power Operation Modes (Z80180-Class Processors Only)

    Z8018x Family MPU User Manual Also, the WAIT input is ignored during RESET. For example, if RESET is detected while the Z8X180 is in a Wait State (TW), the Wait Stated cycle in progress is aborted, and the RESET sequence initiated. Thus, RESET has higher priority than WAIT.
  • Page 46 Z8018x Family MPU User Manual • The HALT output pin is asserted Low • The external bus activity consists of repeated dummy fetches of the Op Code following the HALT instruction. Essentially, the Z80180 operates normally in HALT mode, except that instruction execution is stopped.

  • Page 47: Figure 20. Halt Timing Diagram

    Z8018x Family MPU User Manual Interrupt HALT Op Code HALT mode acknowledge cycle Fetch Cycle INT1, NMI – HALT Op Code address HALT Op Code address + 1 HALT MREQ Figure 20. HALT Timing Diagram SLEEP Mode SLEEP mode is entered by execution of the 2-byte SLP instruction. SLEEP mode contains the following characteristics: •...
  • Page 48 Z8018x Family MPU User Manual • Data Bus, 3-state SLEEP mode is exited in one of two ways as described below. • RESET Exit from SLEEP mode. If the RESET input is held Low for at least six clock cycles, it exits SLEEP mode and begins the normal RESET sequence with execution starting at address (logical and physical) 00000H...

  • Page 49: Figure 21. Sleep Timing Diagram

    Z8018x Family MPU User Manual Op Code Fetch or Interrupt SLP 2nd Op Code SLEEP mode Acknowledge Cycle Fetch Cycle INT1, NMI – SLP 2nd Op Code address FFFFFH HALT Figure 21. SLEEP Timing Diagram IOSTOP Mode IOSTOP mode is entered by setting the IOSTOP bit of the I/O Control Register (ICR) to .

  • Page 50: Low Power Modes (Z8S180/Z8L180 Only)

    Z8018x Family MPU User Manual Low Power Modes (Z8S180/Z8L180 only) The following section is a detailed description of the enhancements to the Z8S180/L180 from the standard Z80180 in the areas of STANDBY, IDLE and STANDBY QUICK RECOVERY modes. Add-On Features There are five different power-down modes.

  • Page 51: Standby Mode

    Z8018x Family MPU User Manual Table 5. Power-Down Modes (Z8S180/Z8L180-Class Processors Only) Power- Down On-Chip Recovery Recovery Time Modes CPU Core Osc. CLKOUT Source (Minimum) SLEEP Stop Running Running Running RESET, 1.5 Clock Interrupts I/O STOP Running Stop Running Running –...

  • Page 52: Standby Mode Exit Wiht Bus Request

    Z8018x Family MPU User Manual 1. Set bits 6 and 3 to , respectively. 2. Set the I/O STOP bits (bit 5 of ICR, I/O Address = ) to 3. Execute the SLEEP instruction. When the device is in STANDBY mode, it performs similar to the SYSTEM STOP mode as it exists on the Z80180-class processors, except that the STANDBY mode stops the external oscillator, internal clocks and reduces power consumption to 50 μA (typical).

  • Page 53: Standby Mode Exit With External Interrupts

    Z8018x Family MPU User Manual If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting the BUSREQ does not cause the Z8S180/Z8L180-class processors to exit STANDBY mode. If STANDBY mode is exited because of a reset or an external interrupt, the Z8S180/Z8L180-class processors remains relinquished from the system bus as long as BUSREQ is active.

  • Page 54: Idle Mode

    Z8018x Family MPU User Manual If the Global Interrupt Enable Flag IEF1 is set to 1, and if an interrupt source is enabled in the ITC, asserting the corresponding interrupt input causes the Z8S180/Z8L180-class processors to exit STANDBY mode. The CPU performs an interrupt acknowledge sequence appropriate to the input being asserted when clocking is resumed if: •...

  • Page 55: Standby-Quick Recovery Mode

    Z8018x Family MPU User Manual except that the 2 bit wake-up timer is bypassed. All control signals are asserted eight clock cycles after the exit conditions are gathered. STANDBY-QUICK RECOVERY Mode STANDBY-QUICK RECOVERY mode is an option offered in STANDBY mode to reduce the clock recovery time in STANDBY mode clock cycles (4 μs at 33 MHz) to 2 clock cycles (1.9 μs at 33 from 2...
  • Page 56 Z8018x Family MPU User Manual To avoid address conflicts with external I/O, the Z8X180 internal I/O addresses can be relocated on 64-byte boundaries within the bottom 256 bytes of the 64KB I/O address space. I/O Control Register (ICR) ICR allows relocating of the internal I/O addresses. ICR also controls enabling/disabling of the IOSTOP mode.

  • Page 57: Figure 22. I/O Address Relocation

    Z8018x Family MPU User Manual 00FFH IOA7 — IOA6 = 1 1 00C0H 00BFH IOA7 — IOA6 = 1 0 0080H 007FH IOA7 — IOA6 = 0 1 0040H 003FH IOA7 — IOA6 = 0 0 0000H Figure 22. I/O Address Relocation Internal I/O Registers Address Map The internal I/O register addresses are described in Table 6 and Table 7.

  • Page 58: Table 6. I/O Address Map For Z80180-Class Processors Only

    Z8018x Family MPU User Manual address to . These instructions are IN0, OUT0, OTIM, OTIMR, OTDM, OTDMR and TSTIO (see Instruction Set). When writing to an internal I/O register, the same I/O write occurs on the external bus. However, the duplicate external I/O write cycle exhibits internal I/O write cycle timing.
  • Page 59 Z8018x Family MPU User Manual Table 6. I/O Address Map for Z80180-Class Processors Only (Continued) Address Register Mnemonic Binary Page Timer Data Register Ch 0 L TMDR0L XX001100 Data Register Ch 0 H TMDR0H XX001101 Reload Register Ch 0 L RLDR0L XX001110 Reload Register Ch 0 H...
  • Page 60 Z8018x Family MPU User Manual Table 6. I/O Address Map for Z80180-Class Processors Only (Continued) Address Register Mnemonic Binary Page DMA Source Address Register Ch 0L SAR0L XX100000 DMA Source Address Register Ch 0H SAR0H XX100001 DMA Source Address Register Ch 0B SAR0B XX100010 DMA Destination Address Register Ch...
  • Page 61 Z8018x Family MPU User Manual Table 6. I/O Address Map for Z80180-Class Processors Only (Continued) Address Register Mnemonic Binary Page IL Register (Interrupt Vector Low XX110011 Register) INT/TRAP Control Register XX110100 Reserved XX110101 Refresh Refresh Control Register XX110110 Reserved XX110111 MMU Common Base Register XX111000 MMU Bank Base Register...

  • Page 62: Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)

    Z8018x Family MPU User Manual Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) Address Register Mnemonic Binary Page ASCI ASCI Control Register A Ch 0 CNTLA0 XX000000 ASCI Control Register A Ch 1 CNTLA1 XX000001 ASCI Control Register B Ch 0 CNTLB0 XX000010 ASCI Control Register B Ch 1...
  • Page 63 Z8018x Family MPU User Manual Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued) Address Register Mnemonic Binary Page Timer Data Register Ch 0 L TMDR0L XX001100 Data Register Ch 0 H TMDR0H XX001101 Reload Register Ch 0 L RLDR0L XX001110 Reload Register Ch 0 H RLDR0H...
  • Page 64 Z8018x Family MPU User Manual Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued) Address Register Mnemonic Binary Page DMA Source Address Register Ch 0L SAR0L XX100000 DMA Source Address Register Ch 0H SAR0H XX100001 DMA Source Address Register Ch 0B SAR0B XX100010 DMA Destination Address Register Ch...
  • Page 65 Z8018x Family MPU User Manual Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued) Address Register Mnemonic Binary Page IL Register (Interrupt Vector Low XX110011 Register) INT/TRAP Control Register XX110100 Reserved XX110101 Refresh Refresh Control Register XX110110 Reserved XX110111 MMU Common Base Register XX111000 MMU Bank Base Register XX111001...
  • Page 66 Z8018x Family MPU User Manual Clock Multiplier Register (CMR: 1EH) (Z8S180/L180-Class Processors Only) Bit/Field Reserved Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Position Bit/Field R/W Value Description X2 Clock X2 Clock Multiplier Mode Multiplier Disable Mode...
  • Page 67 Z8018x Family MPU User Manual CPU Control Register (CCR: 1FH) (Z8S180/L180-Class Processors Only) Bit/Field Clock STAND BREXT LNPHI STAND LNIO LNCPU LNAD/ Divide DATA IDLE IDLE Enable Enable Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Position Bit/Field Value Description Clock...
  • Page 68 Z8018x Family MPU User Manual Position Bit/Field Value Description LNIO Standard Drive 33% Drive on certain external I/O LNCPUCTL Standard Drive 33% Drive on CPU control signals LNAD/ Standard Drive DATA 33% drive on A10–A0, D7–D0 Memory Management Unit (MMU) The Z8X180 features an on-chip MMU which performs the translation of the CPU 64KB (16-bit addresses ) logical memory...

  • Page 69: Figure 23. Logical Address Mapping Examples

    Z8018x Family MPU User Manual Common Common Common Area 1 Area 1 Area 1 Common Area 1 Bank Area Common Bank Area 0 Area Common Area 0 Figure 23. Logical Address Mapping Examples Logical to Physical Address Translation Figure 24 illustrates an example in which the three logical address space portions are mapped into a 1024KB physical address space.

  • Page 70: Figure 24. Physical Address Transition

    Z8018x Family MPU User Manual FFFFFH FFFFH Common Base Common Area 1 Bank Area Bank Base Common Area 0 0000H x y z Logical Address Space 00000H Physical Address Space Figure 24. Physical Address Transition MMU Block Diagram The MMU block diagram is depicted in Figure 25. The MMU translates internal 16-bit logical addresses to external 20-bit physical addresses.

  • Page 71: Figure 26. I/O Address Translation

    Z8018x Family MPU User Manual Whether address translation (Figure 26) takes place depends on the type of CPU cycle as follows. • Memory Cycles Address Translation occurs for all memory access cycles including instruction and operand fetches, memory data reads and writes, hardware interrupt vector fetch, and software interrupt restarts.

  • Page 72: Figure 27. Logical Memory Organization

    Z8018x Family MPU User Manual • MMU Common/Bank Area Register (CBAR) • MMU Common Base Register (CBR) • MMU Bank Base Register (BBR) CBAR is used to define the logical memory organization, while CBR and BBR are used to relocate logical areas within the 1024KB physical address space.

  • Page 73: Figure 28. Logical Space Configuration

    Z8018x Family MPU User Manual FFFFH MMU Common/Bank Area Register Common Area 1 D000H 1 0 1 CFFFH D6 D5 D4 Bank Area MMU Common/Bank Area Register 4000H 3FFFH D3 D2 D1 D0 Common Area 0 0000H Figure 28. Logical Space Configuration (Example) UM005004-0918...

  • Page 74: Mmu Register Description

    Z8018x Family MPU User Manual MMU Register Description MMU Common/Bank Area Register (CBAR) CBAR specifies boundaries within the Z8X180 64KB logical address space for up to three areas; Common Area 0, Bank Area and Common Area 1. MMU Common/Bank Area Register (CBAR: 3AH) Bit/Field Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable...
  • Page 75 Z8018x Family MPU User Manual MMU Common Base Register (CBR) CBR specifies the base address (on 4K boundaries) used to generate a 20- bit physical address for Common Area 1 accesses. All bits of CBR are reset to 0 during RESET. MMU Common Base Register (CBR: 38H) Bit/Field Reset...
  • Page 76 Z8018x Family MPU User Manual MMU Bank Base Register (BBR) BBR specifies the base address (on 4KB boundaries) used to generate a 20-bit physical address for Bank Area accesses. All bits of BBR are reset during RESET. MMU Bank Base Register (BBR: 39H) Bit/Field Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable...
  • Page 77 Z8018x Family MPU User Manual MMU and RESET During RESET, all bits of the CA field of CBAR are set to while all bits of the BA field of CBAR, CBR and BBR are reset to . The logical 64KB address space corresponds directly with the first 64KB 0000H FFFFH...

  • Page 78: Figure 29. Physical Address Generation

    Z8018x Family MPU User Manual MMU Common/ 12 11 Bank Area Logical Register Address D7 — D4 (64K) Comparator MMU Common/ Bank Area Register D3 — D0 MMU Common Base Reg. MMU Bank Base Reg. 0 0 0 0 0 0 0 0 Adder (19) 18 12 11...

  • Page 79: Interrupts

    Z8018x Family MPU User Manual Packages not containing an A19 pin or situations using TOUT Note: instead of A18 yield an address capable of only addressing 512K of physical space. Interrupts The Z8X180 CPU has twelve interrupt sources, 4 external and 8 internal, with fixed priority.
  • Page 80 Z8018x Family MPU User Manual Function Name Access Method Interrupt Vector High LD A,I and LD I, A instructions Interrupt Vector Low I/O instruction (addr = 33H) Interrupt/Trap Control I/O instruction (addr = 34H) Interrupt Enable Flag 1,2 IEF1, IEF2 El and DI Interrupt Vector Register (I) Mode 2 for INT0 external interrupt, INT1 and INT2 external interrupts, and all internal interrupts (except TRAP) use a programmable vectored...
  • Page 81 Z8018x Family MPU User Manual vector table can be relocated on 32 byte boundaries. IL is initialized to during RESET. Interrupt Vector Low Register (IL: 33H) Bit/Field Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Position Bit/Field Value Description...
  • Page 82 Z8018x Family MPU User Manual INT/TRAP Control Register (ITC: 34H) Bit/Field TRAP ITE2 ITE1 ITE0 Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Position Bit/Field Value Description TRAP This bit is set to 1 when an undefined Op Code is fetched. TRAP can be reset under program control by writing it with 0, however, it cannot be written with 1 under program control.

  • Page 83: Table 8. State Of Ief1 And Ief2

    Z8018x Family MPU User Manual If IEF1 is , all maskable interrupts are disabled. IEF1 can be reset to the DI (Disable Interrupts) instruction and set to by the El (Enable Interrupts) instruction. The purpose of IEF2 is to correctly manage the occurrence of NMI. During NMI, the prior interrupt reception state is saved and all maskable interrupts are automatically disabled (IEF1 copied to IEF2 and then IEF1 cleared to...
  • Page 84 Z8018x Family MPU User Manual Table 8. State of IEF1 and IEF2 (Continued) Operation IEF1 IEF2 REMARKS LD A, I not affected not affected Transfers the contents of IEF2 to LID A, R not affected not affected Transfers the contents of IEF2 to TRAP Interrupt The Z8X180 generates a non-maskable (not affected by the state of IEF1) TRAP interrupt when an undefined Op Code fetch occurs.

  • Page 85: Figure 32. Trap Timing Diagram -2Nd Op Code Undefined

    Z8018x Family MPU User Manual stacked PC-1. If UFO is , the starting address of the invalid instruction is equal to the stacked PC-2. Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be inserted just after TTP state which is inserted for TRAP interrupt sequence.

  • Page 86: Figure 33. Trap Timing - 3Rd Op Code Undefined

    Z8018x Family MPU User Manual Restart from 0000H Memory 3rd Op Code Read Cycle Fetch Cycle PC stacking Op Code fetch cycle T1 T2 T3 T1 T2 TTP T1 T2 T1 T2 T3 – SP-1 SP-2 IX+d, IY+d 0000H – Undefined Op Code MREQ...
  • Page 87 Z8018x Family MPU User Manual 1. DMAC operation is suspended by the clearing of the DME (DMA Main Enable) bit in DCNTL. 2. The PC is pushed onto the stack. 3. The contents of IEF1 are copied to IEF2. This saves the interrupt reception state that existed prior to NMI.

  • Page 88: Figure 34. Nmi Use

    Z8018x Family MPU User Manual → → 0066H Main → (SP-1) Program → (SP-2) Interrupt Service Program ← ← (SP) ← RETN (SP+1) Figure 34. NMI Use Last MC NMI acknowledge cycle PC is pushed onto stack Restart from 0066H Op Code fetch T1 T2 –...

  • Page 89: Figure 35. Nmi Timing

    Z8018x Family MPU User Manual Figure 35. NMI Timing INT0 - Maskable Interrupt Level 0 The next highest priority external interrupt after NMI is INT0. INT0 is sampled at the falling edge of the clock state prior to T3 or T1 in the last machine cycle.

  • Page 90: Figure 36. Int0 Mode 0 Timing Diagram

    Z8018x Family MPU User Manual Last MC INT0 acknowledge cycle RST instruction execution PC is pushed onto stack INT0 – SP-1 SP-2 MREQ IORQ RST instruction – MC: Machine Cycle *Two Wait States are automatically inserted Note: The TRAP interrupt occurs if an invalid instruction is fetched during Mode 0 interrupt acknowledge.

  • Page 91: Figure 37. Int0 Mode 1 Interrupt Sequence

    Z8018x Family MPU User Manual disabling all maskable interrupts. The interrupt service routine normally terminates with the EI (Enable Interrupts) instruction followed by the RETI (Return from Interrupt) instruction, to reenable the interrupts. Figure 37 depicts the use of INT0 (Mode 1) and RETI for the Mode 1 interrupt sequence.

  • Page 92: Figure 38. Int0 Mode 1 Timing

    Z8018x Family MPU User Manual INT0 Acknowledge Cycle Op Code Fetch Cycle Last MC PC is pushed onto stack INT0 – 0038H SP-2 SP-1 MREQ IORQ – *Two Wait States are automatically inserted Figure 38. INT0 Mode 1 Timing INT0 Mode 2 This method determines the restart address by reading the contents of a table residing in memory.

  • Page 93: Figure 39. Int0 Mode 2 Vector Acquisition

    Z8018x Family MPU User Manual The vector table address is located on 256 byte boundaries in the 64KB logical address space programmed in the 8-bit Interrupt Vector Register (1). Figure 39 depicts the INT0 Mode 2 Vector acquisition. Memory 16-bit Vector Interrupt Vector 8-bit on Data Bus...

  • Page 94: Figure 40. Int0 Interrupt Mode 2 Timing Diagram

    Z8018x Family MPU User Manual Op Code Last MC Fetch Cycle INT0 Acknowledge Cycle Interrupt Vector Lower Manipulation Address Read PC is pushed onto stack Cycle T2 T3 T2 T3 INT0 Starting address – SP-1 SP-2 Vector Vector+1 MREQ IORQ Starting Address Starting Address (Lower Address)

  • Page 95: Figure 41. Int1, Int2 Vector Acquisition

    Z8018x Family MPU User Manual also the interrupt response sequence used for all internal interrupts (except TRAP). As depicted in Figure 41, the low-order byte of the vector table address has the most significant three bits of the software programmable IL register while the least significant five bits are a unique fixed value for each interrupt (INT1, INT2 and internal) source: Memory...

  • Page 96: Interrupt Acknowledge Cycle Timings

    Z8018x Family MPU User Manual individual I/O (PRT, DMAC, CSI/O, ASCI) control register. The lower vector of INT1 INT2 and internal interrupt are summarized in Table 9. Table 9. Vector Table Fixed Code Interrupt Source Priority INT1 — — — Highest INT2 —...

  • Page 97: Interrupt Sources During Reset

    Z8018x Family MPU User Manual Interrupt Sources During RESET Interrupt Vector Register (I) All bits are reset to . Because I = locates the vector tables starting at logical address vectored interrupts (INT0 Mode 2, INT1, INT2, 0000H and internal interrupts) overlap with fixed restart interrupts like RESET (0), NMI ( ), INT0 Mode 1 ( ) and RST (...

  • Page 98: Figure 42. Reti Instruction Sequence

    Z8018x Family MPU User Manual Return from Subroutine (RETI) Instruction Sequence When the sequence is fetched by the Z8X180, it is recognized as the RETI instruction sequence. The Z8X180 then refetches the RETI instruction with four T-states in the cycle allowing the Z80 peripherals time to decode that cycle (See Figure 42).

  • Page 99: Table 10. Reti Control Signal States

    Z8018x Family MPU User Manual Z8X180. Figure 43 illustrates the INT1, INT2 and internal interrupts timing. Table 10. RETI Control Signal States Machine Cycle States Address Data RD WR MREQ IORQ M1E=1 M1E=0 HALT ST T1-T3 1st Op Code TI-T3 2nd Op Code Don't 3-state...

  • Page 100: Dynamic Ram Refresh Control

    Z8018x Family MPU User Manual Op Code fetch cycle INT1, INT2, internal interrupt acknowledge cycle Last MC Vector Table Read PC Stacking Starting INT1,2 Address – SP-2 Vector SP-1 Vector+1 MREQ IORQ Starting Starting address (L) address (H) – * Two Wait States are automatically inserted. MC: Machine Cycle Figure 43.

  • Page 101: Figure 44. Refresh Cycle Timing Diagram

    Z8018x Family MPU User Manual Refresh cycles may be programmed to be either two or three clock cycles in duration by programming the REFW (Refresh Wait) bit in the Refresh Control Register (RCR). The external WAIT input and the internal Wait State generator are not effective during refresh.
  • Page 102 Z8018x Family MPU User Manual Refresh Control Register (RCR) The RCR specifies the interval and length of refresh cycles, while enabling or disabling the refresh function. Refresh Control Register (RCR: 36H) Bit/Field REFE REFW CYC1 CYC0 Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Position Bit/Field R/W Value Description...

  • Page 103: Table 11. Dram Refresh Intervals

    Z8018x Family MPU User Manual Table 11. DRAM Refresh Intervals Time Interval Insertion CYC1 CYC0 Interval 10 MHz 8 MHz 6 MHz 4 MHz 2.5 MHz μ μ μ μ μ 10 states (1.0 (1.25 1.66 μ μ μ μ μ...

  • Page 104: Dma Controller (Dmac)

    Z8018x Family MPU User Manual 3. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle is requested during SLEEP mode, the refresh cycle request is internally latched (until replaced with the next refresh request). The latched refresh cycle is inserted at the end of the first machine cycle after SLEEP mode is exited.
  • Page 105 Z8018x Family MPU User Manual • DREQ Input Level- and edge-sense DREQ input detection are selectable. TEND Output Used to indicate DMA completion to external devices. • Transfer Rate Each byte transfer occurs every 6 clock cycles. Wait States can be inserted in DMA cycles for slow memory or I/O devices.
  • Page 106 Z8018x Family MPU User Manual Channel 0 • SAR0–Source Address Register • DAR0–Destination Address Register • BCR0–Byte Count Register Channel 1 • MAR1–Memory Address Register • IAR1–I/O Address Register • BCR1–Byte Count Register The two channels share the following three additional registers in common: •...

  • Page 107: Figure 45. Dmac Block Diagram

    Z8018x Family MPU User Manual Internal Address/Data Bus DMA Status DMA Source Address Register : DSTAT (8) Register ch0 : SAR0 (20) DREQ0 Priority & Request DMA Destination Address DMA Mode Control Register ch0 : DAR0 (20) Register : DMODE (8) DREQ1 DMA Byte Count DMA/WAIT Control...
  • Page 108 Z8018x Family MPU User Manual DMA Destination Address Register Channel 0 (DAR0 I/O Address = 23H to 25H) Specifies the physical destination address for channel 0 transfers. The register contains 20 bits and can specify up to 1024KB memory addresses or up to 64KB I/O addresses.
  • Page 109 Z8018x Family MPU User Manual DMA Status Register (DSTAT) DSTAT is used to enable and disable DMA transfer and DMA termination interrupts. DSTAT also determines DMA transfer status, that is, completed or in progress. DMA Status Register (DSTAT: 30H) Bit/Field DWE1 DWE0 DIE1...
  • Page 110 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description Enable Channel 0 — When DE0 = 1 and DME = 1, channel 0 DMA is enabled. When a DMA transfer terminates BCR0 = 0), DE0: is reset to 0 by the DMAC. When DE0 = 0 and the DMA interrupt is enabled (DIE0 = 1), a DMA interrupt request is made to the CPU.
  • Page 111 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description DMA Main Enable — A DMA operation is only enabled when its DE bit DE0 for channel 0, DE1 for channel 1) and the DME bit are set to 1. When NMI occurs, DME is reset to 0, thus disabling DMA activity during the NMI interrupt service routine.

  • Page 112: Table 12. Channel 0 Destination

    Z8018x Family MPU User Manual Position Bit/Field R/W Value Description – SM1:0 Source Mode Channel — Specifies whether the source for channel 0 transfers is memory, I/O, or memory mapped I/O and the corresponding address modifier. Reference Table 13. MMOD DMA Memory Mode Channel 0 —...

  • Page 113: Table 13. Channel 0 Source

    Z8018x Family MPU User Manual Table 13. Channel 0 Source Memory/I/O Address lncrement/Decrement Memory Memory Memory fixed fixed Table 14 describes all DMA TRANSFER mode combinations of DM0 DM1, SM0 SM1. Because I/O to/from I/O transfers are not implemented, 12 combinations are available. Table 14.

  • Page 114: Table 14. Transfer Mode Combinations

    Z8018x Family MPU User Manual Table 14. Transfer Mode Combinations DM1 DM0 SM1 SM0 Transfer Mode Increment/Decrement Memory SAR0+1, DAR0 fixed Memory SAR0-1, DAR0 fixed Reserved Reserved Note: *: includes memory mapped I/O. DMA/WAIT Control Register (DCNTL) DCNTL controls the insertion of Wait States into DMAC (and CPU) accesses of memory or I/O Also, the DMA request mode for each DREQ DREQ0 and DREQ1) input is defined as level or edge sense.
  • Page 115 Z8018x Family MPU User Manual DMA/WAIT Control Register (DCNTL: 32H) Bit/Field MWI1 MWI0 IWI1 IWI0 DMS1 DMS0 DIM1 DIM0 Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Position Bit/Field R/W Value Description – –...

  • Page 116: Table 15. Channel 1 Transfer Mode

    Z8018x Family MPU User Manual Table 15. Channel 1 Transfer Mode DIM1 DIM0 Transfer Mode Address Increment/Decrement Memory MARI +1, IAR1 fixed Memory MARI -1, IAR1 fixed Memory IAR1 fixed, MAR1+1 Memory IAR1 fixed, MAR1-1 DMA I/O Address Register Ch. 1 (IAR1B: 2DH) (Z8S180/L180-Class Processor Only) Bit/Field Reserved Reset...
  • Page 117 Z8018x Family MPU User Manual Position Bit/Field Value Description DMA1 ext TOUT/DREQ DMA1 ASCI0 DMA1 ASCI1 DMA1 ESCC DMA1 PIA27-20 (P1284) DMA Register Description Bit 7 This bit must be set to 1 only when both DMA channels are set to take their requests from the same device.
  • Page 118 Z8018x Family MPU User Manual Bits 5–3 Reserved. Must be 0. Bits 2–0 With DIM1, bit 1 of DCNTL, these bits control which request is presented to DMA channel 1, as described below: DIM1 IAR18–16 Request Routed to DMA Channel 1 DREQ1 ASCI0 Tx ASCI1 Tx...
  • Page 119 Z8018x Family MPU User Manual In addition, the operation of channel 0 DMA with the on-chip ASCI (Asynchronous Serial Communication Interface) as well as Channel 1 DMA are described. Memory to Memory—Channel 0 For memory to/from memory transfers, the external DREQ0 input is not used for DMA transfer timing.

  • Page 120: Figure 46. Dma Timing Diagram-Cycle Steal Mode

    Z8018x Family MPU User Manual DMA cycle CPU cycle DMA cycle (transfer 1 byte) CPU cycle DMA cycle LD g,m Source Destination LD g,m memory operand memory Op Code address address address address Address MREQ Read data Write data, Data Figure 46.

  • Page 121: Figure 47. Cpu Operation And Dma Operation Dreq0 Is Programmed For Level-Sense

    Z8018x Family MPU User Manual Memory to I/O (Memory Mapped I/O) — Channel 0 For memory to/from I/O (and memory to/from memory mapped I/O) the DREQ0 input is used to time the DMA transfers. In addition, the TEND0 (Transfer End) output is used to indicate the last (byte count register BCR0 = ) transfer.

  • Page 122: Figure 48. Cpu Operation And Dma Operation Dreq0 Is Programmed For Edge-Sense

    Z8018x Family MPU User Manual rising edge of the clock prior to T3 at which time the DMA operation (re)starts. Figure 48 depicts the edge-sense DMA timing. Write Machine Read Write Machine Cycle Cycle Cycle Cycle Cycle DREQ0 ** DREQ0 is sampled at Figure 48.
  • Page 123 Z8018x Family MPU User Manual memory mapped I/O. transfers, the CKA0/DREQ0 pin automatically functions as input pin or output pin even if it has been programmed as output pin for CKA0. And the CKA1/TEND0 pin functions as an input or an output pin for TEND0 by setting CKA1D to 1 in CNTLA1.

  • Page 124: Table 16. Dma Transfer Request

    Z8018x Family MPU User Manual DREQ0 for ASCI transmission and reception respectively. To initiate memory to/from ASCI DMA transfer, perform the following operations: 1. Load the source and destination addresses into SAR0 and DAR0 Specify the I/O (ASCI) address as follows: a.
  • Page 125 Z8018x Family MPU User Manual 2. Specify memory ↔ I/O transfer mode and address increment/ decrement in the SM0, SM1, DM0 and DM1 bits of DMODE. 3. Load the number of bytes to transfer in BCR0 4. The DMA request sense mode (DMS0 bit in DCNTL) must be specified as edge sense.
  • Page 126 Z8018x Family MPU User Manual 4. Specify whether DREQ1 is level- or edge- sense in the DMS1 bit in DCNTL. 5. Enable or disable DMA termination interrupt with the DIE1 bit in DSTAT. 6. Program DE1 = (with DWE1 = 0 in the same access) in DSTAT and the DMA operation with the external I/O device begins using the external DREQ1 input and TEND1 output.
  • Page 127 Z8018x Family MPU User Manual cycle is extended to 4 clocks by automatic insertion of one internal Ti state. DMAC Channel Priority For simultaneous DREQ0 and DREQ1 requests, channel 0 has priority over channel 1. When channel 0 is performing a memory to/from memory transfer, channel 1 cannot operate until the channel 0 operation has terminated.

  • Page 128: Figure 50. Dma Interrupt Request Generation

    Z8018x Family MPU User Manual DMAC Internal Interrupts Figure 50 illustrates the internal DMA interrupt request generation circuit. IEF1 DMA ch1 Interrupt Request DIE1 DMA ch0 Interrupt Request DIE0 Figure 50. DMA Interrupt Request Generation DE0 and DE1 are automatically cleared to by the Z8X180 at the completion (byte count is ) of a DMA operation for channel 0 and...

  • Page 129: Asynchronous Serial Communication Interface (Asci)

    Z8018x Family MPU User Manual If the falling edge of NMI occurs before the falling clock of the state prior to T3 (T2 or Tw) of the DMA write cycle, the DMAC is suspended and the CPU starts the NMI response at the end of the current cycle. By setting a channel's DE bit to , the channel's operation is restarted and DMA correctly resumes from its suspended point by NMI.
  • Page 130 Z8018x Family MPU User Manual The key functions for ASCI on Z80180, Z8S180 and Z8L180 class processors are listed below. Each channel is independently programmable. • Full-duplex communication • 7- or 8-bit data length • Program controlled 9th data bit for multiprocessor communication •...

  • Page 131: Figure 52. Asci Block Diagram

    Z8018x Family MPU User Manual Internal Address/Data Bus Interrupt Request ASCI Transmit Data Register ASCI Transmit Data Register ch 1 : TDR1 ch 0 : TDR0 TXA1 TXA0 ASCI Transmit Shift Register* ASCI Transmit Shift Register* ch 0 : TSR0 ch 1 : TSR1 ASCI Receive Data Register ASCI Receive Data Register...
  • Page 132 Z8018x Family MPU User Manual When transmission is completed, the next byte (if available) is automatically loaded from TDR into TSR and the next transmission starts. If no data is available for transmission, TSR idles by outputting a continuous High level. The TSR is not program-accessible. ASCI Transmit Data Register 0, 1(TDR0,1:I/O Address = 06H, 07H) Data written to the ASCI Transmit Data Register is transferred to the TSR as soon as TSR is empty.
  • Page 133 Z8018x Family MPU User Manual ASCI Receive Shift Register 0,1(RSR0, 1) This register receives data shifted in on the RXA pin. When full, data is automatically transferred to the ASCI Receive Data Register (RDR) if it is empty. If RSR is not empty when the next incoming data byte is shifted in, an overrun error occurs.
  • Page 134 Z8018x Family MPU User Manual , data can be written into the ASCII Receive Data Register, and the data can be read. ASCI Status Register 0, 1 (STAT0, 1) Each channel status register allows interrogation of ASCI communication, error and modem control signal status, and enabling or disabling of ASCI interrupts.
  • Page 135 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description Parity Error — PE is set to 1 when a parity error is detected on an incoming data byte and ASCI parity detection is enabled (the MOD1 bit of CNTLA is set to 1).
  • Page 136 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description Transmit Interrupt Enable — TIE must be set to 1 to enable ASCI transmit interrupt requests. If TIE is 1, an interrupt is requested when TDRE is 1. TIE is cleared to 0 during RESET.
  • Page 137 Z8018x Family MPU User Manual ASCI Control Register A0, 1 (CNTLA0, 1) Each ASCI channel Control Register A configures the major operating modes such as receiver/transmitter enable and disable, data format, and multiprocessor communication mode. ASCI Status Register 1 (STAT1: 05H) Bit/Field RDRF OVRN...
  • Page 138 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description Framing Error — If a receive data byte frame is delimited by an invalid stop bit (that is, 0, should be 1), FE is set to 1. FE is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET.
  • Page 139 Z8018x Family MPU User Manual ASCI Control Register A0, 1 (CNTLA0, 1) Each ASCI channel Control Register A configures the major operating modes such as receiver/transmitter enable and disable, data format, and multiprocessor communication mode. ASCI Control Register A 0 (CNTLA0: 00H) Bit/Field RTS0 MPBR/...
  • Page 140 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description Receiver Enable — When RE is set to 1, the ASCI receiver is enabled. When RE is reset to 0, the receiver is disabled and any receive operation in progress is interrupted.
  • Page 141 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description – – MOD2 0 R/W ASCI Data Format Mode 2, 1, 0 — These bits program the ASCI data format as follows. MOD2 0: 7 bit data 1: 8 bit data MOD1 0: No parity 1: Parity enabled...
  • Page 142 Z8018x Family MPU User Manual ASCI Control Register A 1 (CNTLA1: 01H) Bit/Field CKA1D MPBR/ MOD2 MOD1 MOD0 Reset R = Read W = Write X = Indeterminate ? = Not Applicable Position Bit/Field R/W Value Description Multi-Processor Mode Enable — The ASCI has a multiprocessor communication mode which utilizes an extra data bit for selective communication when a number of processors share a common serial bus.
  • Page 143 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description Transmitter Enable — When TE is set to 1, the ASCI transmitter is enabled. When TE is reset to 0, the transmitter is disabled and any transmit operation in progress is interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held.
  • Page 144 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description – – MOD2 0 R/W ASCI Data Format Mode 2, 1, 0 — These bits program the ASCI data format as follows. MOD2 0: 7 bit data 1: 8 bit data MOD1 0: No parity 1: Parity enabled...

  • Page 145: Table 17. Data Formats

    Z8018x Family MPU User Manual Table 17. Data Formats MOD2 MOD1 MOD0 Data Format Start + 7 bit data + 1 stop Start + 7 bit date + 2 Stop Start + 7 bit data + parity + 1 stop Start + 7 bit data + parity + 2 stop Start + 8 bit data + 1 stop Start + 8 bit data + 2 stop...
  • Page 146 Z8018x Family MPU User Manual ASCI Control Register B 0 (CNTLB0: 02H) ASCI Control Register B 1 (CNTLB1: 03H) Bit/Field MPBT CTS/PS Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Position Bit/Field R/W Value Description MPBT...
  • Page 147 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description CTS/PS Clear to Send/Prescale — When read, /PS reflects the state of the external input. If the input pin is High, /PS is read as 1. When the input pin is High, the TDRE bit is inhibited (that is, held at 0).

  • Page 148: Table 18. Divide Ratio

    Z8018x Family MPU User Manual pins are initialized as ASCI data clock inputs. If SS2, SS1 and SS0 are reprogrammed (any other value than SS2, SS1, SS0 = ) these pins become ASCI data clock inputs. However, if DMAC channel 0 is configured to perform memory to/from I/O (and memory mapped I/O) transfers the CKA0/DREQ0 pin reverts to DMA control signals regardless of SS2, SS1, SS0 programming.
  • Page 149 Z8018x Family MPU User Manual ASCI0 Extension Control Register (I/O Address: 12H) (Z8S180/L180-Class Processors Only) Bit/Field RDRF DCD0 CTS0 X1 Bit BRG0 Break Break Send Disable Disable Mode Feature Detect Break Inhibit ASCI0 Enable (RO) Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Position Bit/Field Value Description RDRF...
  • Page 150 Z8018x Family MPU User Manual Position Bit/Field Value Description Send Normal Xmit Break Drive TXA Low Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection. ASCI1 Extension Control Register (I/O Address: 13H) (Z8S180/L180-Class Processors Only) Bit/Field RDRF Reserved...
  • Page 151 Z8018x Family MPU User Manual Position Bit/Field Value Description Break Break Feature Enable On Feature Break Feature Enable Off Enable Break Break Detect On Detect Break Detect Off (RO) Send Normal Xmit Break Drive TXA Low Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection.
  • Page 152 Z8018x Family MPU User Manual ASCI1 Time Constant Low Register (I/O Address: 1CH) (Z8S180/L180-Class Processors Only) Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable ASCI1 Time Constant High Register (I/O Address: 1DH) (Z8S180/L180-Class Processors Only) Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable...

  • Page 153: Figure 53. Dcd0 Timing Diagram

    Z8018x Family MPU User Manual The error flags (PE, FE, and OVRN bits) are also held at . Even after the DCD0 input goes Low, these bits do not resume normal operation until the status register (STAT0, is read. This first read of (STAT0, while enabling normal operation, still indicates the DCD0 input is High (DCD0 bit = 1) even though it has gone Low.

  • Page 154: Figure 54. Rts0 Timing Diagram

    Z8018x Family MPU User Manual I/O Instruction I/O write cycle RTS0 Flag RTS0 Pin Figure 54. RTS0 Timing Diagram Figure 55 illustrates the ASCI interrupt request generation circuit. IEF1 DCD0 RDRF0 OVRN0 RIE0 ASCI0 Interrupt Request TDRE0 TIE0 RDRF1 OVRN1 ASCI1 Interrupt RIE1 Request...

  • Page 155: Figure 56. Asci Clock

    Z8018x Family MPU User Manual ASCI to/from DMAC Operation Operation of the ASCI with the on-chip DMAC channel 0 requires that the DMAC be correctly configured to use the ASCI flags as DMA request signals. ASCI and RESET During RESET, the ASCI status and control registers are initialized as defined in the individual register descriptions.

  • Page 156: Table 19. Asci Baud Rate Selection

    Z8018x Family MPU User Manual Table 19. ASCI Baud Rate Selection Sampling Baud Rate (Example) Prescaler Rate Baud Rate (BPS) General φ = 6.144 φ = 4.608 φ = 3.072 Divide SS2 SS1 SS0 Divide Divide Clock Ratio DR Rate Ratio Ratio Frequency...

  • Page 157: Baud Rate Generator

    Z8018x Family MPU User Manual Table 19. ASCI Baud Rate Selection (Continued) Sampling Baud Rate (Example) Prescaler Rate Baud Rate (BPS) General φ = 6.144 φ = 4.608 φ = 3.072 Divide SS2 SS1 SS0 Divide Divide Clock Ratio DR Rate Ratio Ratio Frequency...

  • Page 158: Table 20. Clock Mode Bit Values

    Z8018x Family MPU User Manual a common baud rate of up to 512 Kbps to be selected. The BRG can also be disabled in favor of an external clock on the CKA pin. The Receiver and Transmitter subsequently divide the output of the BRG (or the signal from the CKA pin) by 1, 16, or 64, under the control of the DR bit in the CNTLB register, and the X1 bit in the ASCI Extension Control REgister.

  • Page 159: Table 21. 2^Ss Values

    Z8018x Family MPU User Manual 2^ss depends on the three least significant bits of the CNTLB register, as described in Table 21. Table 21. 2^ss Values 2^ss External Clock from CKA0 The ASCIs require a 50% duty cycle when CKA is used as an input. Minimum High and Low times on CKA0 are typical of most CMOS devices.

  • Page 160: Clocked Serial I/O Port (Csi/O)

    Z8018x Family MPU User Manual causes for an ASCI Receive interrupt (PE, FE, OVRN, and for ASCI0, DCD) continue to request RX interrupt if the RIE bit is 1. The Rx DMA request is inhibited if PE or FE or OVRN is set, so that software can detect where an error occurred.

  • Page 161: Csi/O Registers Description

    Z8018x Family MPU User Manual Internal Address/Data Bus CSI/O Transmit/Receive Baud Rate Data Register: Generator TRDR (8) CSI/O Control Register: CNTR (8) Interrupt Request Figure 57. CSI/O Block Diagram CSI/O Registers Description CSI/O Control/Status Register (CNTR: I/O Address 0AH) CNTR is used to monitor CSI/O status, enable and disable the CSI/O, enable and disable interrupt generation, and select the data clock speed and source.
  • Page 162 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description End Flag — EF is set to 1 by the CSI/O to indicate completion of an 8-bit data transmit or receive operation. If EIE (End Interrupt Enable) bit = 1 when EF is set to 1, a CPU interrupt request is generated.
  • Page 163 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description Transmit Enable — A CSI/O transmit operation is started by setting TE to 1. When TE is set to 1, the data clock is enabled. When in internal clock mode, the data clock is output from the CKS pin.

  • Page 164: Table 22. Csi/O Baud Rate Selection

    Z8018x Family MPU User Manual CSI/O Transmit/Receive Register (TRDR: 0BH) Bit/Field CSI/O Transmit/Receive Data Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Table 22. CSI/O Baud Rate Selection Divide Ratio Baud Rate ÷ (200000) ÷...

  • Page 165: Figure 58. Csi/O Interrupt Request Generation

    Z8018x Family MPU User Manual IEF1 CSI/O Interrupt Request Figure 58. CSI/O Interrupt Request Generation CSI/O Operation The CSI/O is operated using status polling or interrupt driven algorithms. • Transmit–Polling a. Poll the TE bit in CNTR until TE = b.
  • Page 166 Z8018x Family MPU User Manual c. Poll the RE bit in CNTR until RE = d. Read the receive data from TRDR. e. Repeat steps 2 to 4 for each receive data byte. • Receive–Interrupts a. Poll the RE bit in CNTR until RE is b.

  • Page 167: Figure 59. Transmit Timing Diagram-Internal Clock

    Z8018x Family MPU User Manual CSI/O and RESET During RESET each bit in the CNTR is initialized as defined in the CNTR register description. CSI/O transmit and receive operations in progress are aborted during RESET. However, the contents of TRDR are not changed.

  • Page 168: Figure 60. Transmit Timing-External Clock

    Z8018x Family MPU User Manual 2.5φ 2.5φ 2.5φ 2.5φ 7.5φ 7.5φ 7.5φ 7.5φ Read or write of CSI/O Transmit/Receive Data Register Figure 60. Transmit Timing–External Clock UM005004-0918...

  • Page 169: Figure 61. Csi/O Receive Timing-Internal Clock

    Z8018x Family MPU User Manual 11φ 11φ 11φ 11φ Sampling 17φ Read or write of CSI/O Transmit/Receive Data Register Figure 61. CSI/O Receive Timing–Internal Clock UM005004-0918...

  • Page 170: Programmable Reload Timer (Prt)

    Z8018x Family MPU User Manual 11.5φ 11.5φ 11.5φ 11.5φ 16.5φ 16.5φ 16.5φ 16.5φ Sampling Read or write of CSI/O Transmit/Receive Data Register Figure 62. CSI/O Receive Timing–External Clock Programmable Reload Timer (PRT) The Z8X180 contains a two channel 16-bit Programmable Reload Timer. Each PRT channel contains a 16-bit down counter and a 16-bit reload register.

  • Page 171: Figure 63. Prt Block Diagram

    Z8018x Family MPU User Manual control register. The PRT input clock for both channels is equal to the system clock divided by 20. Internal Address/Data Bus Phi ÷ 20 Phi ÷ 20 Timer Data Timer Data Timer Data Timer Data Register 0L Register 1L Register 0H...
  • Page 172 Z8018x Family MPU User Manual return accurate data without requiring the timer to be stopped. The write procedure requires the PRT to be stopped. For reading (without stopping the timer), TMDR is read in the order of lower byte - higher byte (TMDRnL, TMDRnH). The lower byte read (TMDRnL) stores the higher byte value in an internal register.
  • Page 173 Z8018x Family MPU User Manual Timer Data Register 0L (TMDR0L: 0CH) Bit/Field Timer Data Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Data Register 0H (TMDR0H: 0DH) Bit/Field Timer Data Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Reload Register (RLDR: I/O Address = CH0: 0EH, 0FH, CHI, 16H, 17H) PRT0 and PRT1 each contain 16-bit Timer Reload Registers (RLDR).
  • Page 174 Z8018x Family MPU User Manual Timer Reload Register Channel 0L (RLDR0L: 0EH) Bit/Field Timer Reload Data Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Reload Register Channel 0H (RLDR0L: 0FH) Bit/Field Timer Reload Data Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Data Register 1L (TMDR1L: 14H)
  • Page 175 Z8018x Family MPU User Manual Timer Reload Register Channel 1L (RLDR1L: 16H) Bit/Field Timer Reload Data Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Reload Register Channel 1H (RLDR1H: 17H) Bit/Field Timer Reload Data Reset Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Control Register (TCR)
  • Page 176 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description – – TIF1 TIF1: Timer Interrupt Flag — When TMDR1 decrements to 0, TIF1 is set to 1. This generates an interrupt request if enabled by TIE1 = 1. TIF1 is reset to 0 when TCR is read and the higher or lower byte of TMDR1 is read.

  • Page 177: Table 23. Timer Output Control

    Z8018x Family MPU User Manual Table 23. Timer Output Control TOC1 TOC0 OUTPUT Inhibited (A18/TOUT pin is selected as an address output function.) Toggled A18/TOUT pin is selected as a PRT1 output function! Figure 64 illustrates timer initialization, count down, and reload timing. Figure 65 depicts timer output (A18/TOUT) timing.

  • Page 178: Figure 65. Timer Output Timing Diagram

    Z8018x Family MPU User Manual Timer Data Timer Data Reg. = 0000H Reg. = 0001H TOUT Figure 65. Timer Output Timing Diagram PRT Interrupts The PRT interrupt request circuit is illustrated in Figure 66. IEF1 PRT1 Interrupt TIF1 Request TIE1 PRT0 Interrupt TIF0 Request...
  • Page 179 Z8018x Family MPU User Manual PRT Operation Notes • TMDR data is accurately read without stopping down counting by reading the lower (TMDRnL*) and higher (TMDRnH*) bytes in that order. Also, TMDR is read or written by stopping the down counting.

  • Page 180: Table 24. E Clock Timing In Each Condition

    Z8018x Family MPU User Manual These devices require connection with the Z8X180 synchronous E clock output. The speed (access time) required for the peripheral devices are determined by the Z8X180 clock rate. Table 24, and Figure 67 through Figure 70 define E clock output timing. Wait States are inserted in Op Code fetch, memory read/write, and I/O read/write cycles which extend the duration of E clock output High.

  • Page 181: Figure 67. E Clock Timing Diagram

    Z8018x Family MPU User Manual Op Code Memory Read/ Acknowledge INT0 Acknowledge Fetch Cycle Write Cycle I/O Read Cycle I/O Write Cycle 1st MC 1st MC T1 T2 T3 MREQ IORQ NOTE : MC = Machine Cycle * Two wait states are automatically inserted Figure 67.

  • Page 182: Figure 69. E Clock Timing In Sleep Mode And

    Z8018x Family MPU User Manual Instruction Op Code 2nd Op Code Fetch Cycle Fetch Cycle SLEEP mode or SYSTEM STOP mode – INT, NMI Figure 69. E Clock Timing in SLEEP Mode and SYSTEM STOP Mode On-Chip Clock Generator The Z8X180 contains a crystal oscillator and system clock generator. A crystal can be directly connected or an external clock input can be provided.

  • Page 183: Figure 70. External Clock Interface

    Z8018x Family MPU User Manual Table 25. Z8X180 Operating Frequencies Clock Frequency Item < ≤ < ≤ 4MHz 12MHz 12MHz 33MHz 4MHz < < < 7 pF 7 pF 7 pF < Ω < Ω < Ω ± ± ± CL1, CL2 10 to 22 pF 10 to 22 pF...

  • Page 184: Figure 71. Clock Generator Circuit

    Z8018x Family MPU User Manual XTAL EXTAL Z8X180 Note: Pin numbers are valid only for DIP configuration Figure 71. Clock Generator Circuit Must be avoided A, B Signal Signal C Z8X180 Figure 72. Circuit Board Design Rules UM005004-0918...

  • Page 185: Figure 73. Example Of Board Design

    Z8018x Family MPU User Manual Signal line layout must 20 mm max avoid shaded areas Crystal Z8X180 Note: Pin mumbers valid only for DIP configuration Top View Figure 73. Example of Board Design Circuit Board design should observe the following parameters. •...

  • Page 186: Miscellaneous

    Z8018x Family MPU User Manual Miscellaneous Free Running Counter (I/O Address = If data is written into the free running counter, the interval of DRAM refresh cycle and baud rates for the ASCI and CSI/O are not guaranteed. In IOSTOP mode, the free running counter continues counting down. It is initialized to during RESET.

  • Page 187: Software Architecture

    Z8018x Family MPU User Manual Software Architecture INSTRUCTION SET The Z80180 is object code-compatible with the Z80 CPU. Refer to the Z80 CPU Technical Manual or the Z80 Assembly Language Programming Manual for further details. Table 26. Instruction Set Summary New Instructions Operation Enter SLEEP mode 8-bit multiply with 16-bit result...
  • Page 188 Z8018x Family MPU User Manual MLT- Multiply The MLT performs unsigned multiplication on two 8-bit numbers yielding a 16-bit result. MLT may specify BC, DE, HL, or SP registers. The 8-bit operands are loaded into each half of the 16-bit register and the 16-bit result is returned in that register.

  • Page 189: Cpu Registers

    Z8018x Family MPU User Manual TST (HL) - Test Memory The contents of memory pointed to by HL are ANDed with the accumulator (A) and the status flags are updated. The memory contents and accumulator are not changed (non-destructive AND). INO g, (m) - Input, Immediate I/O address The contents of immediately specified 8-bit I/O address are input into the specified register.

  • Page 190: Figure 74. Cpu Register Configurations

    Z8018x Family MPU User Manual Figure 74 depicts CPU register configurations. Register Set GR Accumulator A Flag Register F B Register C Register General D Register E Register Purpose Registers H Register L Register Register Set GR' Accumulator A' Flag Register F' B' Register C' Register General...
  • Page 191 Z8018x Family MPU User Manual Flag Registers (F, F') The flag registers store status bits (described in the next section) resulting from executed instructions. General Purpose Registers (BC, BC', DE, DE', HL, HL') The General Purpose Registers are used for both address and data operation.
  • Page 192 Z8018x Family MPU User Manual Stack Pointer (SP) The Stack Pointer (SP) contains the memory address based LIFO stack. SP is cleared to during reset. 0000H Program Counter (PC) The Program Counter (PC) contains the address of the instruction to be executed and is automatically updated after each instruction fetch.
  • Page 193 Z8018x Family MPU User Manual Position Bit/Field R/W Value Description Zero. Z is set to 1 when instruction execution produces 0 result. Otherwise, Z is reset to 0. Not Used ? Not used Half Carry. H is used by the DAA (Decimal Adjust Accumulator) instruction to reflect borrow or carry from the least significant 4 bits and thereby adjust the results of BCD addition and subtraction.
  • Page 194 Z8018x Family MPU User Manual Addressing Modes The Z80180 instruction set includes eight addressing modes. • Implied Register • Register Direct • Register Indirect • Indexed • Extended • Immediate • Relative • Implied Register (IMP) Certain Op Codes automatically imply register usage, such as the arithmetic operations that inherently reference the Accumulator, Index Registers, Stack Pointer, and General Purpose Registers.

  • Page 195: Figure 75. Register Direct - Bit Field Definitions

    Z8018x Family MPU User Manual 8-bit Register g or g field ' Register ww field Register 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 xx field Register — 1 1 0 1 1 1 16-bit Register yy field Register...

  • Page 196: Figure 77. Indexed Addressing

    Z8018x Family MPU User Manual Indexed (INDX) The memory operand address is calculated using the contents of an Index Register (IX or IY) and an 8-bit signed displacement specified in the instruction. Refer to Figure 77 Op Code 1 Op Code 2 displacement (d) Operand Memory...

  • Page 197: Figure 79. Immediate Addressing

    Z8018x Family MPU User Manual Immediate (IMMED) The memory operands are contained within one or two bytes of the instruction, as depicted in Figure 79. Op Code Op Code 8-bit 16-bit operand operand Figure 79. Immediate Addressing Relative (REL) Relative addressing mode is only used by the conditional and unconditional branch instructions (refer to Figure 80).
  • Page 198 Z8018x Family MPU User Manual IO (I/O) IO addressing mode is used only by I/O instructions. This mode specifies I/O address (IORQ is ) and outputs them as follows. 1. An operand is output to A0–A7. The contents of accumulator is output to A8–A15.

  • Page 199: Dc Characteristics

    Z8018x Family MPU User Manual DC Characteristics This section describes the DC characteristics of the Z8X180 family and absolute maximum rating for these products. ABSOLUTE MAXIMUM RATING Table 27. Absolute Maximum Rating Item Symbol Value Unit - 0.3 ∼ + 7.0 Supply Voltage -0.3 ∼...

  • Page 200: Z80180 Dc Characteristics

    Z8018x Family MPU User Manual Z80180 DC CHARACTERISTICS = 5V ± 10%, V = OV, Ta = 0° to +70°C, unless otherwise noted.) Table 28. Z80180 DC Characteristics Symbol Item Condition Minimum Typical Maximum Unit VIH1 Input High Voltage –0.6 – +0.3 RESET, EXTAL NMI VIH2...

  • Page 201: Z8S180 Dc Characteristics

    Z8018x Family MPU User Manual Table 28. Z80180 DC Characteristics (Continued) Symbol Item Condition Minimum Typical Maximum Unit Power Dissipation* f = 6 MHz – 12.5 (SYSTEM STOP mode) f = 8 MHz – 15.0 f = 33 MHz – 17.5 Pin Capacitance VIN = 0V, f = 1MHz...
  • Page 202 Z8018x Family MPU User Manual Table 29. Z8S180 DC Characteristics (Continued) Symbol Item Condition Minimum Typical Maximum Unit IOH = –200 μA VOH1 Output High Voltage – – IOH = –20 μA All outputs –1.2 – – IOH = –200 μA VOH2 Output High Voltage –0.6 Output High Phi...

  • Page 203: Z8L180 Dc Characteristics

    Z8018x Family MPU User Manual Z8L180 DC CHARACTERISTICS = 3.3V ± 10%, V = OV, Ta = 0° to +70°C, unless otherwise noted.) Table 30. Z8L180 DC Characteristics Symbol Item Condition Minimum Typical Maximum Unit VIH1 Input High Voltage –0.6 –...
  • Page 204 Z8018x Family MPU User Manual Table 30. Z8L180 DC Characteristics (Continued) Symbol Item Condition Minimum Typical Maximum Unit Power Dissipation* f = 20 MHz (Normal Operation) Power Dissipation* f = 20 MHz (SYSTEM STOP Mode) Power Dissipation* f = 20 MHz (IDLE Mode) μA Power Dissipation*...
  • Page 205 Z8018x Family MPU User Manual Z8L180 Typical ICCA at 4 MHz (Volts) Z8S180 Typical ICCA at 20 MHz (Volts) UM005004-0918...
  • Page 206 Z8018x Family MPU User Manual UM005004-0918...

  • Page 207: Ac Characteristics

    Z8018x Family MPU User Manual AC Characteristics This section describes the AC characteristics of the Z8X180 family and absolute maximum rating for these products. AC CHARACTERISTICS—Z8S180 Table 31. Z8S180 AC Characteristics V = 5V ±10% or V = 3.3V ±10%; 33-MHz Characteristics Apply Only to 5V Operation Z8S180—20 Z8S180—33 Symbol Item...

  • Page 208: Table 31. Z8S180 Ac Characteristics

    Z8018x Family MPU User Manual Table 31. Z8S180 AC Characteristics (Continued) V = 5V ±10% or = 3.3V ±10%; 33-MHz Characteristics Apply Only to 5V Z8S180—20 Z8S180—33 Symbol Item Unit PHI Fall to RD Rise Delay — — RDD2 PHI Rise to M1 Rise Delay —...
  • Page 209 Z8018x Family MPU User Manual Table 31. Z8S180 AC Characteristics (Continued) V = 5V ±10% or = 3.3V ±10%; 33-MHz Characteristics Apply Only to 5V Z8S180—20 Z8S180—33 Symbol Item Unit NMI Pulse Width — — NMIW BUSREQ Set-up Time to PHI Fall —...
  • Page 210 Z8018x Family MPU User Manual Table 31. Z8S180 AC Characteristics (Continued) V = 5V ±10% or = 3.3V ±10%; 33-MHz Characteristics Apply Only to 5V Z8S180—20 Z8S180—33 Symbol Item Unit CSI/O Transmit Data Delay Time — — tcyc STDI (Internal Clock Operation) CSI/O Transmit Data Delay Time —...

  • Page 211: Timing Diagrams

    Z8018x Family MPU User Manual Timing Diagrams I/O Write Cycle* I/O Read Cycle* Opcode Fetch Cycle ADDRESS WAIT MREQ IORQ Data IN Data OUT RESET Figure 81. AC Timing Diagram 1 UM005004-0918...

  • Page 212: Figure 82. Ac Timing Diagram 2

    Z8018x Family MPU User Manual Memory Read/Write Cycle timing is the sam as I/O Read/Write Cycle except there are no automatica Wait States (TW), and MREQ is active instead of IORQ. INT0,1,2 IORQ Data IN MREQ RFSH BUSREQ BUSACK A19–0, D7–0 MREQ, RD WR, IORQ Output Buffer Off...
  • Page 213 Z8018x Family MPU User Manual I/O Write Cycle I/O Read Cycle ADDRESS IORQ I/O Read Cycle CPU Timing (IOC = 0) I/O Write Cycle Figure 83. CPU Timing (IOC = 0) (I/O Read Cycle, I/O Write Cycle) UM005004-0918...

  • Page 214: Figure 84. Dma Control Signals

    Z8018x Family MPU User Manual CPU or DMA Read/Write Cycle (Only DMA Write Cycle for TENDi) DREQ1 (level sense) DREQ1 (edge sense) CPU Cycle Starts DMA Cycle TENDi Starts Notes: and T are specified for the rising edge of the clock followed by T DRQS DRQH and T...

  • Page 215: Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle)

    Z8018x Family MPU User Manual (Memory Read/Write) (I/O Read) (I/O Write) –D Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle) BUS RELEASE mode SLEEP mode SYSTEM STOP mode Figure 86. E Clock Timing (BUS RELEASE Mode, SLEEP Mode, and SYSTEM STOP Mode UM005004-0918...

  • Page 216: Figure 87. E Clock Timing

    Z8018x Family MPU User Manual Example I/O Read → Opcode Fetch (I/O Write) Figure 87. E Clock Timing (Minimum Timing Example of PWEL and PWEH) Timer Data Reg. = 0000H A18/T Figure 88. Timer Output Timing UM005004-0918...

  • Page 217: Figure 89. Slp Execution Cycle Timing Diagram

    Z8018x Family MPU User Manual Next Opcode Fetch SLP Instruction Fetch INTi –A MREQ, M1 HALT Figure 89. SLP Execution Cycle Timing Diagram UM005004-0918...

  • Page 218: Figure 90. Csi/O Receive/Transmit Timing Diagram

    Z8018x Family MPU User Manual CSI/O Clock Transmit Data (Internal Clock) Transmit Data (External Clock) Receive Data (Internal Clock) 16.5t 11.5t 11.5t 16.5t Receive Data (External Clock) Figure 90. CSI/O Receive/Transmit Timing Diagram EXTAL VIL1 VIH1 VIH1 VIL1 Figure 91. External Clock Rise Time and Fall Time RESET Figure 92.

  • Page 219: Standard Test Conditions

    Z8018x Family MPU User Manual STANDARD TEST CONDITIONS The previous DC Characteristics and Capacitance sections apply to the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Positive current flows in to the referenced pin. All AC parameters assume a load capacitance of 100 pF.
  • Page 220 Z8018x Family MPU User Manual UM005004-0918...

  • Page 221: Instruction Set

    Z8018x Family MPU User Manual Instruction Set This section explains the symbols in the instruction set. REGISTER g, g', ww, xx, yy, and zz specify a register to be used. g and g' specify an 8-bit register. ww, xx, yy, and zz specify a pair of 8-bit registers. Table 32 describes the correspondence between symbols and registers.

  • Page 222: Condition

    Z8018x Family MPU User Manual Table 33. Bit Values CONDITION f specifies the condition in program control instructions. Table 34 describes the correspondence between f and conditions. Table 34. Instruction Values Condition Nonzero Zero Non Carry Carry Parity Odd Parity Even Sign Plus Sign Minus UM005004-0918...

  • Page 223: Restart Address

    Z8018x Family MPU User Manual RESTART ADDRESS v specifies a restart address. Table 35 describes the correspondence between v and restart addresses. Table 35. Address Values Address FLAG The symbols listed in Table 36 indicate the flag conditions. Table 36. Flag Conditions Not Affected •...

  • Page 224: Miscellaneous

    Z8018x Family MPU User Manual MISCELLANEOUS Table 37 lists the operations mnemonics. Table 37. Operations Mnemonics Data in the memory address Data in the I/O address m or n 8-bit data 16-bit data 8-bit register 16-bit register b.( ) A content of bit b in the memory address b.gr A content of bit b in the register gr d or j 8-bit signed displacement...

  • Page 225: Data Manipulation Instructions

    Z8018x Family MPU User Manual DATA MANIPULATION INSTRUCTIONS Table 38. Arithmetic and Logical Instructions (8-bit) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N C ↑ ↑ ↑ V R ↑...
  • Page 226 Z8018x Family MPU User Manual Table 38. Arithmetic and Logical Instructions (8-bit) (Continued) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N C AND g 10 100 g Ar*gr→Ar ↑...
  • Page 227 Z8018x Family MPU User Manual Table 38. Arithmetic and Logical Instructions (8-bit) (Continued) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N C DEC g 00 g 101 gr-1→gr ↑...
  • Page 228 Z8018x Family MPU User Manual Table 38. Arithmetic and Logical Instructions (8-bit) (Continued) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N C OR g 10 110 g Ar + gr→Ar ↑...
  • Page 229 Z8018x Family MPU User Manual Table 38. Arithmetic and Logical Instructions (8-bit) (Continued) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N C SUBC SBC A,g 10 011 g Ar-gr-c→Ar ↑...
  • Page 230 Z8018x Family MPU User Manual Table 38. Arithmetic and Logical Instructions (8-bit) (Continued) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N C XOR (IY + d) 11 111 101 →Ar ↑...

  • Page 231: Table 39. Rotate And Shift Instructions

    Z8018x Family MPU User Manual Table 39. Rotate and Shift Instructions (Continued) Flags Addressing 7 6 4 2 Operation State Name Mnemonics Op Code Immed Ext Ind Reg Regi Imp Rel Bytes Operation S Z H P/V N C RLC (IX + d) 11 011 101 ↑...
  • Page 232 Z8018x Family MPU User Manual Table 39. Rotate and Shift Instructions (Continued) Flags Addressing 7 6 4 2 Operation State Name Mnemonics Op Code Immed Ext Ind Reg Regi Imp Rel Bytes Operation S Z H P/V N C 11 001 011 <d>...
  • Page 233 Z8018x Family MPU User Manual Table 39. Rotate and Shift Instructions (Continued) Flags Addressing 7 6 4 2 Operation State Name Mnemonics Op Code Immed Ext Ind Reg Regi Imp Rel Bytes Operation S Z H P/V N C SRL (HL) 11 001 011 ↑...
  • Page 234 Z8018x Family MPU User Manual Table 39. Rotate and Shift Instructions (Continued) Flags Addressing 7 6 4 2 Operation State Name Mnemonics Op Code Immed Ext Ind Reg Regi Imp Rel Bytes Operation S Z H P/V N C • • • • •...

  • Page 235: Table 40. Arithmetic Instructions (16-Bit)

    Z8018x Family MPU User Manual Table 40. Arithmetic Instructions (16-bit) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation P/V N C ADD HL,ww 00 ww1 001 + ww →HL • • •...

  • Page 236: Data Transfer Instructions

    Z8018x Family MPU User Manual DATA TRANSFER INSTRUCTIONS Table 41. 8-Bit Load Flags Addressing 7 6 4 2 Operation Name Mnemonics Op Code Immed Ext RegI Imp Bytes States Operation S Z H P/V Load LD A,I 11 101 101 1r→Ar ↑...
  • Page 237 Z8018x Family MPU User Manual Table 41. 8-Bit Load (Continued) Flags Addressing 7 6 4 2 Operation Name Mnemonics Op Code Immed Ext RegI Imp Bytes States Operation S Z H P/V Load LD (IX + d),m 11 011 101 S m→(IX + d) •...

  • Page 238: Table 42. 16-Bit Load

    Z8018x Family MPU User Manual Table 42. 16-Bit Load (Continued) Flags Addressing 7 6 4 2 Operation Name Mnemonics Op Code Immed Reg RegI Imp Rel Bytes States Operation S Z H P/V N C • • • • • • Load LD IY,mn 11 111 101...

  • Page 239: Table 43. Block Transfer

    Z8018x Family MPU User Manual Table 42. 16-Bit Load (Continued) Flags Addressing 7 6 4 2 Operation Name Mnemonics Op Code Immed Reg RegI Imp Rel Bytes States Operation S Z H P/V N C Load LD (mn),HL 00 100 010 Hr→(mn + 1) •...
  • Page 240 Z8018x Family MPU User Manual Table 43. Block Transfer (Continued) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N C ↑ ↑ ↑ ↑ S • 11101101 Ar-(HL) 10100001 -1→BC + 1→HL CPIR...

  • Page 241: Table 44. Stock And Exchange

    Z8018x Family MPU User Manual Table 44. Stock and Exchange Flags Addressing 7 6 4 2 Operation Name Mnemonics Op Code Immed Ext Reg RegI Imp Rel Bytes States Operation S Z H P/V N C • • • • •...
  • Page 242 Z8018x Family MPU User Manual Table 44. Stock and Exchange (Continued) Flags Addressing 7 6 4 2 Operation Name Mnemonics Op Code Immed Ext Reg RegI Imp Rel Bytes States Operation S Z H P/V N C • • • • •...

  • Page 243: Program And Control Instructions

    Z8018x Family MPU User Manual PROGRAM AND CONTROL INSTRUCTIONS Table 45. Program Control Instructions Flags Addressing 7 6 4 2 Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation S Z H P/V N C •...
  • Page 244 Z8018x Family MPU User Manual Table 45. Program Control Instructions (Continued) Flags Addressing 7 6 4 2 Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation S Z H P/V N C • • • • •...

  • Page 245: Table 46. I/O Instructions

    Z8018x Family MPU User Manual Table 46. I/O Instructions Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N INPUT IN A,(m) 11 011 011 (Am)1,→Ar • • • • •...
  • Page 246 Z8018x Family MPU User Manual Table 46. I/O Instructions (Continued) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N 14 (Br ≠ 0) →(HL) ↑ INPUT INIR 11 101 101 (BC) + 1→HL 10 110 010...
  • Page 247 Z8018x Family MPU User Manual Table 46. I/O Instructions (Continued) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N OUTPUT OTDR 11 101 101 14 (Br ≠ 0) (HL) →(BC) ↑...
  • Page 248 Z8018x Family MPU User Manual Table 46. I/O Instructions (Continued) Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation H P/V N 16 (Br ≠ 0) →(00C) ↑ OTIMR** 11 101 101 (HL) + 1→HL 10 010 011...

  • Page 249: Special Control Instructions

    Z8018x Family MPU User Manual Special Control Instructions Table 47. Special Control Instructions Flags Addressing 7 6 4 2 Operation Name Mnemonics Op Code Immed Ext Ind Reg Regi Bytes States Operation S Z H P/V N C ↑ ↑ ↑ P •...
  • Page 250 Z8018x Family MPU User Manual UM005004-0918...

  • Page 251: Instruction Summary

    Z8018x Family MPU User Manual Instruction Summary ** : Added new instructions to Z80 Machine MNEMONICS Bytes Cycles States ADC A,m ADC A,g ADC A, (HL) ADC A, (IX+d) ADC A, (IY+d) ADD A,m ADD A,g ADD A, (HL) ADD A, (IX+d) ADD A, (IY+d) ADC HL,ww ADD HL,ww...
  • Page 252 Z8018x Family MPU User Manual Machine MNEMONICS Bytes Cycles States (If condition is true) CALL mn CPDR ≠ ≠ (If BC 0 and Ar (HL) (If BC = 0 or Ar = (HL) CP (HL) CPIR ≠ ≠ (If BC 0 and Ar (HL) (If BCR = 0 or Ar = (HL)
  • Page 253 Z8018x Family MPU User Manual Machine MNEMONICS Bytes Cycles States 7 (if Br EX AF,AF' EX DE,HL EX (SP),HL EX (SP)I,IX EX (SP),IY HALT IM 0 IM 1 IM 2 INC g INC (HL) INC (IX+d) INC (IY+d) INC ww INC IX INC IY IN A,(m)
  • Page 254 Z8018x Family MPU User Manual Machine MNEMONICS Bytes Cycles States (If f is true) JP (HL) JP (IX) JP (IY) JP mn JR j JR C,j (If condition is false) (If condition is true) JR NC,j (if condition is false) (If condition is true) JR Z,j (If condition is false)
  • Page 255 Z8018x Family MPU User Manual Machine MNEMONICS Bytes Cycles States LD (DE),A LD ww,mn LD ww,(mn) ≠ LDDR 14 (If BC 12 (If BC LD (HL),m LD HL,(mn) LD (HL),g LDI,A ≠ LDIR 14 (If BC 12 (If BC = 0) LD IX,mn LID IX,(mn) LD (IX+d),m...
  • Page 256 Z8018x Family MPU User Manual Machine MNEMONICS Bytes Cycles States LD g,g' LD SP,HL LD SP,IX LD SP,IY MLT ww" OR (HL) OR (IX+d) OR (IY+d) OR m OR g OTDM** ≠ OTDMR** 16 (If Br 14 (If Br = 0) ≠...
  • Page 257 Z8018x Family MPU User Manual Machine MNEMONICS Bytes Cycles States PUSH IX PUSH IY PUSH zz RES b,(HL) RES b,(IX+d) RES b,(IY+d) RES b,g RET f (If condition is false) (If condition is true) RETI 4 (R0, R1) 12 (R0, R1) 10 (Z) 22 (Z) RETN...
  • Page 258 Z8018x Family MPU User Manual Machine MNEMONICS Bytes Cycles States RRC (IY+d) RRC g RR (HL) RR (IX+d) RR (IY+d) RR g RST v SBC A,(HL) SBC A, (IX+d) SBC A,(IY+d) SBC A,m SBC A,g SBC HL,ww SET b,(HL) SET b,(IX+d) SET b,(IY+d) SET b,g SLA (HL)
  • Page 259 Z8018x Family MPU User Manual Machine MNEMONICS Bytes Cycles States SRL (IY+d) SRL g SUB (HL) SUB (IX+d) SUB (IY+d) SUB m SUB g **TSTIO m **TST g TST m** TST (HL)** XOR (HL) XOR (IX+d) XOR (IY+d) XOR m XOR g UM005004-0918...
  • Page 260 Z8018x Family MPU User Manual UM005004-0918...

  • Page 261: Op Code Map

    Z8018x Family MPU User Manual Op Code Map Table 48. 1st Op Code Map Instruction Format: XX ww (L0 = ALL) L0 = 0~7 g (LO = 0~7) (HL) (HL) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100...
  • Page 262 Z8018x Family MPU User Manual Note 1: (HL) replaces g. Note 2: (HL) replaces s. Note 3: If DDH is supplemented as first Op Code for the instructions which have HL or (HL) as an operand in Table 48, the instructions are executed replacing HL with IX and (HL) with (IX+d).

  • Page 263: Table 49. 2Nd Op Code Map Instruction Format: Cb Xx

    Z8018x Family MPU User Manual Table 49. 2nd Op Code Map Instruction Format: CB XX b (L0 = 0~7) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 RLC g RL g SLA g 0010 0011...

  • Page 264: Table 50. 2Nd Op Code Map Instruction Format: Ed Xx

    Z8018x Family MPU User Manual Table 50. 2nd Op Code Map Instruction Format: ED XX ww (L0 = ALL) G (L0 = 0~7) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 IN0 g, (m) IN g, (C) LDIR...

  • Page 265: Bus Control Signal Conditions

    Z8018x Family MPU User Manual Bus Control Signal Conditions BUS AND CONTROL SIGNAL CONDITION IN EACH MACHINE CYCLE * (ADDRESS) invalid Z (DATA) high impedance. ** added new instructions to Z80 Table 51. Bus and Control Signal Condition in Each Machine Cycle Machine Instruction Cycle...
  • Page 266 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST ADD A,g T1T2T3 1st Op Code 1st Op ADC A,g Address Code SUB g...
  • Page 267 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST AND (IY+ d) TiTiTi OR (IX + d) ~MC6 OR (IY+d) XOR (IX + d) XOR (IY+d) CP (IX+d)
  • Page 268 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 1st operand Address CALL mn T1T2T3 2nd operand...
  • Page 269 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op Address Code...
  • Page 270 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code DJNZ j Ti*2 (If Br ≠...
  • Page 271 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op EX (SP),IX Address...
  • Page 272 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op INC (IX+ d) Address...
  • Page 273 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op IN g,(C) Address...
  • Page 274 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code INIR T1T2T3 2nd Op Code 2nd Op INDR Address...
  • Page 275 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 1st operand JR j Address MC3~M...
  • Page 276 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op Address Code...
  • Page 277 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op Address Code...
  • Page 278 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 1st operand Address LD (mn),A T1T2T3 2nd operand...
  • Page 279 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 1st operand Address LD HL, (mn) T1T2T3 2nd operand...
  • Page 280 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 1st operand Address LD (mn),HL T1T2T3 2nd operand...
  • Page 281 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op Address Code...
  • Page 282 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op LDIR Address...
  • Page 283 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 1st operand OUT (m),A Address T1T2T3 m to A0~A7...
  • Page 284 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op Address Code...
  • Page 285 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op Address Code...
  • Page 286 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code OTIR T1T2T3 2nd Op Code 2nd Op OTDR Address...
  • Page 287 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op Address Code...
  • Page 288 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op Address Code...
  • Page 289 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op RLC (HL) Address Code RL (HL) T1T2T3 2nd Op Code 2nd Op...
  • Page 290 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code TiTi RST v ~MC3 T1T2T3 SP-1 T1T2T3 SP-2...
  • Page 291 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code T1T2T3 2nd Op Code 2nd Op Address Code...
  • Page 292 Z8018x Family MPU User Manual Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 1st Op Code 1st Op Address Code TST g** T1T2T3 2nd Op Code 2nd Op Address...

  • Page 293: Interrupts

    Z8018x Family MPU User Manual INTERRUPTS Table 52. Interrupts Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2T3 Next Op Code Address (PC) T1T1 ~MC3 T1T2T3 SP-1 T1T2T3 SP-2 T1T2TW Next Op 1st (PC) TWT3 Code Op Code INT0 Mode 0...

  • Page 294: Table 52. Interrupts

    Z8018x Family MPU User Manual Table 52. Interrupts (Continued) Machine Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST T1T2TW Next Vector TWT3 Op Code Address (PC) INT0 Mode 2 T1T2T3 SP-1 T1T2T3 SP-2 T1T2T3 I, Vector DATA T1T2T3 I, Vector+1...

  • Page 295: Operating Modes Summary

    Z8018x Family MPU User Manual Operating Modes Summary REQUEST ACCEPTANCES IN EACH OPERATING MODE Table 53. Request Acceptances in Each Operating Mode Current Normal Status Operation (CPU mode Interrupt SYSTEM and IOSTOP Refresh Acknowledge RELEASE SLEEP STOP Request Mode) WAIT State Cycle Cycle DMA Cycle...

  • Page 296: Request Priority

    Z8018x Family MPU User Manual Table 53. Request Acceptances in Each Operating Mode Current Normal Status Operation (CPU mode Interrupt SYSTEM and IOSTOP Refresh Acknowledge RELEASE SLEEP STOP Request Mode) WAIT State Cycle Cycle DMA Cycle Mode Mode Mode Internal ↑...

  • Page 297: Operation Mode Transition

    Z8018x Family MPU User Manual Note: If Bus Request and Refresh Request occur simultaneously, Bus Request is accepted but Refresh Request is cleared. OPERATION MODE TRANSITION NORMAL *1 RESET = 0 HALT RESET SYSTEM SLEEP STOP IOSTOP UM005004-0918...
  • Page 298 Z8018x Family MPU User Manual NORMAL *1 RESET = 0 RESET REFRESH RELEASE Figure 94. Operation Mode Transition * 1. NORMAL: CPU executes instructions normally in NORMAL mode. * 2. DMA request: DMA is requested in the following cases. – DREQ0, DREQ1 = 0 memory to/from (memory mapped) I/0 DMA transfer –...

  • Page 299: Other Operation Mode Transitions

    Z8018x Family MPU User Manual – DREQ0, DREQ1 = 1 memory to/from (memory mapped) I/O DMA transfer – BCR0, BCR1 = (all DMA transfers) 0000H – NMI = 0 (all DMA transfers) OTHER OPERATION MODE TRANSITIONS The following operation mode transitions are also possible. HALT REFRESH BUS RELEASE...
  • Page 300 Z8018x Family MPU User Manual UM005004-0918...

  • Page 301: Status Signals

    Z8018x Family MPU User Manual Status Signals PIN OUTPUTS IN EACH OPERATING MODE Table 55 describes pin outputs in each operating mode. Table 55. Pin Outputs in Each Operating Mode Address Data Mode M1 MREQ IORQ RD WR RFSH HALT BUSACK ST Op Code Fetch Operation (1st Op Code)

  • Page 302: Pin Status

    Z8018x Family MPU User Manual Table 55. Pin Outputs in Each Operating Mode (Continued) Address Data Mode M1 MREQ IORQ RD WR RFSH HALT BUSACK ST Memory Read Internal Memory Write I/O Read I/O Write RESET • 1 : High •...

  • Page 303: Table 56. Pin Status During Reset And Low Power Operation Modes

    Z8018x Family MPU User Manual Table 56. Pin Status During RESET and LOW POWER OPERATION Modes Pin Status in Each Operation Mode SYSTEM Symbol Pin Function RESET SLEEP IOSTOP STOP WAIT — IN (N) IN (N) IN (A) IN (N) BUSACK —...
  • Page 304 Z8018x Family MPU User Manual Table 56. Pin Status During RESET and LOW POWER OPERATION Modes (Continued) Pin Status in Each Operation Mode SYSTEM Symbol Pin Function RESET SLEEP IOSTOP STOP CKA0 IN (A) IN (N) IN (N) (External Clock Mode) DREQ0 IN (N) IN (A)
  • Page 305 Z8018x Family MPU User Manual Table 56. Pin Status During RESET and LOW POWER OPERATION Modes (Continued) Pin Status in Each Operation Mode SYSTEM Symbol Pin Function RESET SLEEP IOSTOP STOP MREQ — ← ← — E Clock Output — —...
  • Page 306 Z8018x Family MPU User Manual UM005004-0918...

  • Page 307: I/O Registers

    Z8018x Family MPU User Manual I/O Registers INTERNAL I/O REGISTERS By programming IOA7 and IOA6 as the I/O control register, internal I/O register addresses are relocatable within ranges from 0000H 00FFH the I/O address space. Table 57. Internal I/O Registers Register Mnemonics Address Remarks...

  • Page 308: Table 57. Internal I/O Registers

    Z8018x Family MPU User Manual Table 57. Internal I/O Registers (Continued) Register Mnemonics Address Remarks ASCI Control Register B CNTLB0 CTS/ MPBT Channel 0: invalid during RESET Clock Source and Speed Select Divide Ratio Parity Even or Odd Clear to send/Prescale Multi Processor Multi Processor Bit Transmit * CTS: Depending on the condition 0f CTS Pin.
  • Page 309 Z8018x Family MPU User Manual Table 57. Internal I/O Registers (Continued) Register Mnemonics Address Remarks ASCI Status Channel 0: STAT0 RDRF OVRN DCD0 TDRE during RESET invalid Transmit Interrupt Enable Transmit Data Register Empty Data Carrier Detect Receive Interrupt Enable Framing Error Parity Error Overrun Error...
  • Page 310 Z8018x Family MPU User Manual Table 57. Internal I/O Registers (Continued) Register Mnemonics Address Remarks ASCI Transmit Data TDR0 Register Channel 0: ASCI Transmit Data TDR1 Register Channel 1: ASCI Receive Data TSR0 Register Channel 0: ASCI Receive Data TSR1 Register Channel 1: CSI/O Control Register: CNTR...
  • Page 311 Z8018x Family MPU User Manual Table 57. Internal I/O Registers (Continued) Register Mnemonics Address Remarks CSI/O Transmit/ TRDR Receive Data Register: Timer Data Register TMDR0L Channel 0L: Timer Data Register TMDR0H Channel 0H: Timer Reload Register RLDR0L Channel 0L: Timer Reload Register RLDR0H Channel 0H: Timer Control Register...
  • Page 312 Z8018x Family MPU User Manual Table 57. Internal I/O Registers (Continued) Register Mnemonics Address Remarks Timer Data Register TMDR1L Channel 1L: Timer Data Register TMDR1H Channel 1H: Timer Reload Register RLDR1L Channel 1L Timer Reload Register RLDR1H Channel 1H: Free Running Counter: Read only DMA Source Address SAR0L...
  • Page 313 Z8018x Family MPU User Manual Table 57. Internal I/O Registers (Continued) Register Mnemonics Address Remarks DMA Memory Address MAR1B Bits 0 - 2 are used for MAR1B Register Channel 1B: DMA I/O Address Register IAR1L Channel 1L: DMA I/O Address Register IAR1H Channel 1H DMA Byte Count Register...
  • Page 314 Z8018x Family MPU User Manual Table 57. Internal I/O Registers (Continued) Register Mnemonics Address Remarks MMU Common Base Register: during RESET MMU Common Base Register MMU Bank Base Register during RESET MMU Bank Base Register MMU Common/Bank CBAR Register during RESET MMU Bank Area Register MMU Common Area Register...
  • Page 315 Z8018x Family MPU User Manual Table 57. Internal I/O Registers (Continued) Register Mnemonics Address Remarks DMA/WAIT Control DCNTL Register: DIMA1 DIMA0 MWI1 MWI0 IWI1 IWI0 DMS1 DMS0 during RESET DMA Ch 1 I/O Memory Mode Select DREQi Select, i=1,0 I/O Wait Insertion Memory Wait Insertion The number of The number of...
  • Page 316 Z8018x Family MPU User Manual Table 57. Internal I/O Registers (Continued) Register Mnemonics Address Remarks Interrupt Vector Low Register — — — — — during RESET Interrupt Vector Low INT/TRAP Control TRAP — — — ITE2 ITE1 ITE0 Register during RESET INT Enable 2,1,0 Unidentified Fetch Object TRAP...

  • Page 317: Ordering Information

    08 = 8 MHz 10 = 10 MHz • Environmental C = Plastic Standard • Example Z8018008PSC is an 80180 8 MHz, Plastic DIP, 0°C to 70°C, Plastic Standard Flow. 80180 Environmental Flow Temperature Package Speed Product Number ZiLOG Prefix UM005004-0918...

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