Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
48

Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)

Register
ASCI ASCI Control Register A Ch 0
ASCI Control Register A Ch 1
ASCI Control Register B Ch 0
ASCI Control Register B Ch 1
ASCI Status Register Ch 0
ASCI Status Register Ch 1
ASCI Transmit Data Register Ch 0
ASCI Transmit Data Register Ch 1
ASCI Receive Data Register Ch 0
ASCI Receive Data Register Ch 1
ASCI0 Extension Control Register 0
ASCI1 Extension Control Register 1
ASCI0 Time Constant Low
ASCI0 Time Constant High
ASCI1 Time Constant Low
ASCI1 Time Constant High
CSI0 CSI0 Control Register
CSI0 Transmit/Receive Data Register
UM005004-0918
Mnemonic Binary
CNTLA0 XX000000
CNTLA1 XX000001
CNTLB0 XX000010
CNTLB1 XX000011
STAT0 XX000100
STAT1 XX000101
TDR0 XX000110
TDR1 XX000111
RDR0 XX001000
RDR1 XX001001
ASEXT0 XX010010
ASEXT1 XX010011
ASTC0L XX011010
ASTC0H XX001011
ASCT1L XX001100
ASCT1H XX001101
CNTR XX001010
TRD XX1011
Address
Hex Page
00H 125
01H 128
02H 132
03H 132
04H 120
05H 123
06H 118
07H 118
08H 119
09H 119
12H 135
13H 136
1AH 137
1BH 137
1CH 138
1DH 138
0AH 147
0BH 149