ZiLOG Z8018 Series User Manual page 315

Table 57.
Register
DMA/WAIT Control
Register:
Internal I/O Registers (Continued)
Mnemonics Address
DCNTL 3 2
Family MPU User Manual
Remarks
MWI1 MWI0 IWI1
bit
1 1 1
during RESET
R/W
R/W R/W R/W
Memory Wait Insertion
The number of
wait states
MWI1,0
0 0 0
0 1 1
2
1 0
1 1 3
DMSi Sense
1 Edge sense
0 Level sense
Transfer Mode
DIM1,0
M→I/O
0 0
M→I/O
0 1
1 0 I/O→M
I/O→M
1 1
Z8018x
DIMA1 DIMA0
IWI0 DMS1 DMS0
1 0 0 0
R/W R/W R/W R/W
DREQi Select, i=1,0
I/O Wait Insertion
The number of
wait states
IWI1,0
0 0 0
0 1 2
3
1 0
1 1 4
Address Increment/Decrement
MAR1+1 IAR1 fixed
MAR1-1 IAR1 fixed
IAR1 fixed MAR1+1
IAR1 fixed MAR1-1
UM005004-0918
301
0
R/W
DMA Ch 1
I/O Memory
Mode Select