Table 10. Reti Control Signal States - ZiLOG Z8018 Series User Manual

Mpu
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Z8X180. Figure 43 illustrates the INT1, INT2 and internal interrupts
timing.
Table 10.
RETI Control Signal States
Machine
Cycle
States Address Data
1
T1-T3 1st
Op Code
2
TI-T3 2nd
Op Code
3
T1
Don't
Care
4
T1
Don't
Care
5
T1
Don't
Care
6
T1-T3 1st
Op Code
7
T1
Don't
Care
8
T1-T3 2nd
Op Code
9
T1-T3 SP
10
T1-T3 SP+1
IOC affects the IORQ/RD signals. M1E affects the assertion of M1. One state also reflects a 1 while
the other reflects a 0
RD WR MREQ IORQ
EDH
0
1
4DH
0
1
3-state
1
1
3-state
1
1
3-state
1
1
EDH
0
1
3-state
1
1
4DH
0
1
data
0
1
data
0
1
Family MPU User Manual
MI
M1E=1 M1E=0 HALT ST
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
0
1
0
0
1
1
0
1
1
Z8018x
85
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
UM005004-0918

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