ZiLOG Z8018 Series User Manual page 313

Table 57.
Register
DMA Memory Address
Register
Channel 1B:
DMA I/O Address Register
Channel 1L:
DMA I/O Address Register
Channel 1H
DMA Byte Count Register
Channel 1L:
DMA Byte Count Register
Channel 1H:
DMA Status Register:
DMA Mode Register:
Internal I/O Registers (Continued)
Mnemonics Address
MAR1B 2 A
IAR1L 2 B
IAR1H 2 C
BCR1L 2 E
BCR1H 2 F
DSTAT 3 0
DMODE 3 1
Family MPU User Manual
Remarks
Bits 0 - 2 are used for MAR1B
DE1 DE0 DWE1
bit
during RESET 0
0 1
R/W W
R/W R/W
DMA enable ch 1,0
— — DM1
bit
during RESET
1
1 0
R/W
R/W
DM1,0 Destination
Address
0 0 M
DAR0+1
0 1
M
DAR0-1
1 0 M
DAR0 fixed
I/O
1 1
DAR0 fixed
MMOD Mode
Cycle Steal Mode
0
1 Burst Mode
Z8018x
DWE0 DIE1 DIE0 — DME
R/W
1 0 0 1 0
W R/W R
DMA Interrupt Enable 1,0
DMA Enable Bit Write Enable 1,0
DM0 SM1 SM0 MMOD —
0 0 0 0 1
R/W R/W R/W R/W
Memory MODE select
Ch 0 Source Mode 1,0
Ch 0 Destination Mode 1,0
Source
SM1,0
Address
0 0 M
SAR0+1
0 1 M
SAR0-1
M
1 0
SAR0 fixed
I/O
1 1
SAR0 fixed
UM005004-0918
299
DMA Master enable