ZiLOG Z8018 Series User Manual page 257

MNEMONICS
PUSH IX
PUSH IY
PUSH zz
RES b,(HL)
RES b,(IX+d)
RES b,(IY+d)
RES b,g
RET
RET f
RETI
RETN
RLA
RLCA
RLC (HL)
RLC (IX-1-dl
RLC (IY+d)
RLC g
RLD
RL (HL)
RL (IX+d)
RL (IY+d)
RL g
RRA
RRCA
RRC (HL)
RRC (IX+d)
Family MPU User Manual
Machine
Bytes Cycles
2 6
2 6
1 5
2 5
4 7
4 7
2 3
1 3
1 3
1 4
2 4 (R0, R1) 12 (R0, R1)
10 (Z)
2 4
1 1
1 1
2 5
4 7
4 7
2 3
2 8
2 5
4 7
4 7
2 3
1 1
1 1
2 5
4 7
Z8018x
States
14
14
11
13
19
19
7
9
5
(If condition is false)
10
(If condition is true)
22 (Z)
12
3
3
13
19
19
7
16
13
19
19
7
3
3
13
19
UM005004-0918
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