ZiLOG Z8018 Series User Manual page 277

Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction Cycle
MC1
MC2
LD (IX+d),m
LD (IY+d),m
MC3
MC4
MC5
MC1
LD A, (BC)
LD A, (DE)
MC2
MC1
MC2
LD A,(mn)
MC3
MC4
MC1
LD (BC),A
MC2
LD (DE),A
MC3
States Address Data
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st operand d
Address
T1T2T3 2nd operand m
Address
T1T2T3 IX+ d DATA
IY+d
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 BC DATA
DE
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 1st operand n
Address
T1T2T3 2nd operand m
Address
T1T2T3 mn DATA
T1T2T3 1st Op Code 1st Op
Address Code
Ti * Z
T1T2T3 BC A
DE
Family MPU User Manual
RD WR MREQ IORQ M1 HALT ST
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
1 0 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
1 1 1 1
1 0 0 1
Z8018x
263
0 1 0
0 1 1
1 1 1
1 1 1
1 1 1
0 1 0
1 1 1
0 1 0
1 1 1
1 1 1
1 1 1
0 1 0
1 1 1
1 1 1
UM005004-0918