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Z8018x
Family MPU User Manual
300
Register
MMU Common Base
Register:
MMU Bank Base Register
MMU Common/Bank
Register
Operation Mode Control
Register
I/O Control Register:
UM005004-0918
Table 57.
Internal I/O Registers (Continued)
Mnemonics Address
CBR
3
BBR
3
CBAR
3
OMCR
3
ICR
3
8
CB7
CB6
bit
0
0
during RESET
R/W
R/W
R/W
9
BB7
BB6
bit
0
0
during RESET
R/W
R/W
R/W
A
CA3
CA2
bit
1
1
during RESET
R/W
R/W
R/W
E
MIE
MITE
bit
1
1
during RESET
R/W
W
R/W
M1 Enable
F
IOA7
IOA6
bit
0
0
during RESET
R/W
R/W
R/W
I/O Address
Remarks
CB5
CB4
CB3
CB2
CB1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
MMU Common Base Register
BB5
BB4
BB3
BB2
BB1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
MMU Bank Base Register
CA1
CA0
BA3
BA2
BA1
1
1
0
0
R/W
R/W
R/W
R/W
R/W
MMU Common Area Register
IOC
—
—
—
1
1
1
1
R/W
I/O Compatibility
M1 Temporary Enable
IOSTP
—
—
—
0
1
1
1
R/W
I/O Stop
CB0
0
0
R/W
BB0
0
0
R/W
BA0
0
0
R/W
MMU Bank
Area Register
—
—
1
1
—
—
1
1
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Do you have a question about the Z8018 Series and is the answer not in the manual?
Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated