Figure 16. Bus Exchange Timing During Memory Read - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
26
A0
D0
MREQ
RD, WR
BUSREQ
BUSACK
UM005004-0918
When the bus is released, the address (A0–A19), data (D0–D7), and
control (MREQ, IORQ, RD, and WR) signals are placed in the high
impedance state.
Dynamic RAM refresh is not performed when the Z8X180 has released
the bus. The alternate bus master must provide dynamic memory
refreshing if the bus is released for long periods of time.
Figure 16 illustrates BUSREQ/BUSACK bus exchange during a memory
read cycle. Figure 17 illustrates bus exchange when the bus release is
requested during a Z8X180 CPU internal operation. BUSREQ is sampled
at the falling edge of the system clock prior to T3, T1 and Tx (BUS
RELEASE state). If BUSREQ is asserted Low at the falling edge of the
clock state prior to Tx, another Tx is executed.
CPU memory read cycle
T1 T2
Phi
–
A19
–
D7
IORQ
Figure 16. Bus Exchange Timing During Memory Read
Bus release cycle
TW T3 TX
CPU cycle
TX T1 T1