1. Manuals
  2. Brands
  3. ZiLOG Manuals
  4. Computer Hardware
  5. Z80-AIO
  6. Hardware user manual

ZiLOG Z80-AIO Hardware User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Z80-AIO/AIB
Hardware User's Manual
Zilog

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Z80-AIO and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for ZiLOG Z80-AIO

Summary of Contents for ZiLOG Z80-AIO

  • Page 1 Z80-AIO/AIB Hardware User's Manual Zilog...
  • Page 2 Revision A May 1978 Copyright ©1978 by Zilog, Inc. All rights reserved. No Zilog assumes no responsibility for the use of any circuitry other than circuitry embodied in a Zilog product. No other circuit patent licenses are implied.
  • Page 3 HARDWARE USER'S MANUAL 780428 REVISION A...
  • Page 5 Please take the time to fill out this questionnaire and return it to us. This information will be helpful to us, and, in time, to the future users of Zilog Systems. Thank you.
  • Page 6 First Class Permit No. 475 California 95014 No Postage Necessary if Mailed in the United States Postage Will Be Paid By Software Department Librarian 10460 Bubb Road Cupertino, California 95014...

  • Page 7: Table Of Contents

    Z80-AIO USER SECTION PAGE GENERAL INFORMATION Product Description Block Diagram 2 . 0 INSTALLATION Initial Unpacking and Inspection Installation (MCZ-1) Power and Signal Connections OPERATION Introduction Description Address Modification Application PROGRAMMING AND INITIALIZATION Introduction 4 . 3 Output Programming TESTING...

  • Page 8: Section Page

    SECTION PAGE TECHNICAL DESCRIPTION Introduction Spec if ication 7 . 0 MAINTENANCE Introduction Drift 8 . 0 DRAWINGS Introduction 9 . 0 SUPPLEMENTARY INFORMATION Introduction List of Supplementary Information...

  • Page 9: General Information

    SECTION 1; GENERAL INFORMATION 1.1 Product Description The Z80-AIO is a 12-bit analog input/output card, compatible with the Z80 Microcoinputer Board Series. The analog to digital portion can accept 16 differential or 32 single-ended channels with input voltages ranging The digital to analog portion provides two, 12-bit D/A Converters with double buffering to minimize output switching transients.

  • Page 10: Installation

    SECTION 2: INSTALLATION 2.1 Introduction The following section contains Information on initial to the MCB, and Installation of the AIO Board or AIB in the MCZ l series Systems. 2.2 Initial Unpacking and Inspection Inspect the product for shipping damage äs soon äs it is unpacked.

  • Page 11: Power And Signal Connections

    2.4 Power and Signal Connections The Z80 AIO and AIB are pin-compatible with the Z80 MCB For convenience, the wire list for interconnection between the MCB and the Analog Boards is DESCRIPTION MCB:l-3, 59-61 +5V P.S. AIO:4 IORQ- AIO:5 DATA BIT (5) Next IEI AIO:6 IEO of AIO/AIB...

  • Page 12: Operation

    SECTION 3: OPERATION 3.1 Introduction Operation, and provides some application Software for 3.2 Description by the on-board PIO and is addressed äs I/O. The ADDRESS DECODER uses ten addresses to direct all board operations. By selecting the PIO port A or B control addresses, the PIO Interrupt vector address upon completion of an A/D The CONTROL and TIMING will gate the requested analog input channel to the ANALOG MULTIPLEXER, strobe the...

  • Page 13: Address Modification

    3.3 Address Modifikation The AIO or AIB Interfaces to the Z80 MCB I/O bus, occupying ten locations in the I/O address space. The first four The next two locations are used to transfer the input channel address and board Status while the remaining locations are used for passing data to the two D/A Converters.

  • Page 14: Input/Output Handling

    ADDRESS BIT HIGH JP39 JP38 JP41 JP40 JP30 JP31 JP32 JP27 JP26 JP28 JP29 ADDRESS BIT HIGH JP37 JP36 JP34 JP35 JP32 JP33 JP27 JP26 JP28 JP29 TABLE 3.3.3. Register Address Selection Jumpers 3.4 Input/Output Handling These modes operate äs follows: Interrupt enable flag must be reset to prevent the generation of Interrupts.

  • Page 15: Application

    therefore, eliminates spiking in the Output Signal. 3.5 Application 3.5.1 Input Range Selection The data acquisition System has been jumpered for (+/-)10V Operation. RANGE (+/-)10V (+/-)5V 0 to +10V JP23, JP21, JP25, JP43 0 to +5V JP23, JP20, JP21, JP25, JP43 TABLE 3.5.1.1.
  • Page 16 (#54) drill. JUMPERS RANGE DAC l DAC 2 (+/-)10V JP11, W2* JP15, W4*, JP13 0 to +10V JP11, JP8 JP15, JP12 0 to +5V JP11, JP8, JP9 JP15, JP12, JP13 Output Range Selection Jumpers. When converting from bipolar to unipolar Operation, W5* Bipolar - Two's Complement Digital Input/Output (+/-)10V...
  • Page 17 Operation by making a "pseudo differential" connection. This involves sensing the ground at the signal source rather than To use this method, all input Signals must be on the sanie ground System at their source. been removed and JPl is installed. 3.5.4 Input System Low Level Operation When it is desired to operate the input systein instrumentation amplifier at other than unity gain for low...
  • Page 18 FIGURE 3.5.5.1. On Channel Multiplexer Circuit for For a gain of l (set at factory), multiplexer settling time The only external factor which affects the multiplexer settling time A circuit roodel of an "Cn" channel is shown in The input capacitance (Cl) of 50pF for The Signal at the Output of the multiplexer must be allowed to settle to accuracy of the System.
  • Page 19 For switchinq of large Signals, it must be remembered that the on resistance is the channel resistance of a FET which IF a nonlinear function of the applied voltaqes. As a result, the previous calculations are only an approximation derived from a linearized mode.
  • Page 20 barrier strip may be monitored to allow the observed Figure 3.5.6.2 shows a circuit for this purpose. The Output is connected to one of the input channels to supply ambient Output sensitivity is approximately 2 mV/deg C.
  • Page 21 Thermocouple CHN R 7 N Earth Ground Isothermal 100M Pass Filter FIGURE 3.5.6.1: Thermocouple Input System + 15 I / 1 0 ( R ü l! Rh) ~ ~ Rc + Rd (' Rh ) it; '" T = °K, k/q = 8.67 x 10 Dual monohthii transistor pair (National LM l 14) Barner Strip FIGURE 3.5.6.2:...

  • Page 22: Programming And Initialization

    PIO. A detailed description of the PIO's Operation can be found in the Zilog Z80-PIO Product Specification. Normal Operation of the board reauires programming the PIO äs Polling Mode - Both A and B Mode Control registers must be set for input (mode 1) .
  • Page 23 Interrupt Mode - As in the Polling Mode, the A and B Mode Control Registers must be set for Input (Mode 1). The PIO Interrupt System is enabled by loading the interrupt vector address and setting the interrupt enable. interrupt enable should be set. The following program illustrates the procedure.

  • Page 24: Output Programming

    Output Programming As shown in Table 3.3.1, the two digital to analog Converters occupy locations 8CH - 8FH. Either Converter is programmed by loading the least significant eight bits of data into its The most significant four bits of data are then loaded into the right most bit locations of the The most significant four bits of this byte are unused.

  • Page 25: Testing

    SECTION 5: TESTING 5.1 Introduction The following section contains Information on suggested test equipment and test aids, calibration procedure, and a description of the available calibration and test routines for the AIO and AIB on the MCZ-1. 5.2 Test Equipment and Aids Calibration is performed by connecting a precision voltage source capable of 0.005% accuracy or by using a DC voltage source of less absolute accuracy, the Output of which is...

  • Page 26: Calibration

    5.3 Calibration The program assumes that the Polling Mode initialization has been performed äs described in the Programming section. LD D, 64H LD A, 0 OUT 88H, A IN A, 89H AND 01H JP NZ, AC IN A, 80H LD L, A IN A, 81H LD A, L SUB REF...
  • Page 27 The offset adjustment is made at -10V + 2.44mV = -9.9976V and the gain adjustment at +10V -7.32mV = +9.9926V. Before making these adjustments, however, the unit 30 minutes under power). The offset adjustment is made first. The calibration program is then run, and after 100 conversions, it will halt at the break point.
  • Page 28 Output System Calibration The Output System is calibrated through the use of the following program. START: LD A, LSB LSB = FFH FOR GAIN ADJ. OUT (DACL),A LD A, MSB MSB = OH FOR UNIPOLAR OFFSET MSB = 7H FOR BIPOLAR GAIN MSB = OFH FOR UNIPOLAR GAIN OUT (DACH), A JP START...
  • Page 29 After the Offset adjustment has been made, the appropriate values of LSB and MSB for Gain adjustment must be deposited into the program. The previous procedure must then be repeated, but adjust the gain control for the most positive Range High l LSB (+/-)10V...

  • Page 30: System Test

    5.4 System Test The following tests are provided with the Analog Board and are applicable to the operating Systems available in the The test's titles and descriptions are given in the table below. Test l - DAG l Bilpolar Offset Description negative Output.
  • Page 31 Test 5 - DAC 2 Bipolar Offset This test is performed in the same manner äs Test 1. Test 6 - DAC 2 Bipolar Gain This test is performed in the same manner äs Test 2. gain control for DAC 2 is RV2. Test 7 - DAC 2 Unipolar Offset This test is performed in the same manner äs Test 5.
  • Page 32 Test 9 - Data Acauisition - Bipolar Offset The offset adjustment is made at the most negative value of the selected ränge less one-half the least significant bit. The values are shown for the selected ränge in the Data Acguisition Calibration Table 5.3.1. The test will check the actual conversion value against the expected conversion value "Turn Control Counter Clockwise".
  • Page 33 Test 13 - Generate Ramp DAC l This test generates a ramp from a chronological sequence exercising the DAC to its minimum and maximum values of the conversion ränge. The test is intended for observation only and does not imply that monotinicity and linearity can be measured or accurately observed with Standard laboratory Test 14 - Generate Ramp DAC 2 This test is the same äs Test 13 and applies to DAC 2.
  • Page 34 Test 16 - Bipolar Continuity Test - Interrupt Mode This test operates in the same manner äs Test 15, except that Note: To use Test 16, the interrupt enable input to the interrupt daisy chain.

  • Page 35: Technical Description

    SECTION 6: The following section contains a detailed description of the Operation and logical throughput of the AIO. The reader is directed to use the accompanying schematic at the end of the The AIB, being a subset of the AIO, is not noticeably discriminated in the description.
  • Page 36 The analog input Signals are connected at connectors P2 and P3 through input protection resistors R27-R58 to the input CMOS itiultiplexers, IC3, 4, 5, and 6. The input multiplexers are shipped connected äs 16 channel differential. Instrumentation amplifier, which consists of amplifiers AI, A2, and A3, is connected in the differential mode.

  • Page 37: Specification

    ANALOG INPUT SECTION (AIO/AIB) 32 single-ended/16 diff 0-5V, 0-10V, (+/-) 2.5V, ADC Gain Ranges (Jumper Selectable) (+/-) 5V, (+/-) 10V l to 1000 +26 volts Input Impedance 20 nA Bias Current Differential Bias Current 10 nA Transfer Characteristics Resolution 12 bits 45 usec/channel Throughput Time (max.) G = l Accuracy...
  • Page 38 l ohm Transfer Characteristics 12 bits Resolution 10 usec Output Settling Time (max.) Accuracy Output Accuracy +30 ppm of FSR/deg C Odeg C to +70deg C Operating Temperature -25deg C to +85deg C Storage Temperature 95% noncondensing Relative Humidity Mechanical 7.7 in/19.6 cm 7.5 in/19.1 cm .062 in/0.16 cm...
  • Page 39 Connectors PART NO. DESCRIPTIQN VENDOR 4000-2 (100 mil spacing) Augat 14005-19P1 122-pin edge (100 mil spacing) Analog edge Ansley 171-26 Ansley 609-255 Analog socket Ansley NOTES 1. Includes offset errors, gain errors, linearity errors at gain = 1. 2. FSR mean Füll Scale Range. 3.

  • Page 40: Maintenance

    7.1 Introduction analog boards. 7.2 Drift In any System, powered on Operation will cause the components to drift from their original values. evident in analog Systems. The Eurr-Brown components, used on the AIO and AIB, use thin-film laser-trimmed resisters parts per million and a ratio temperature coefficient of 3-5 parts per million.

  • Page 41: Drawings

    8.1 Introduction This section contains the scheraatic pinout lists and the...
  • Page 42 J Jjj* l l l l i IM» i.
  • Page 44 AIO EDGE ANSLEY "D" P3 SIGNALS CONNECTOR CONNECTOR P2 SIGNALS — REMOTE COMMON REMOTE COMMON -15V + 15V ANALOG COMMON ANALOG COMMON ANALOG COMMON ANALOG COMMON ANALOG COMMON ANALOG COMMON CH24 (RT8) SM1-FB CH15 ANALOG COMMON SM2-GND CH12 SM1-OUT CH13 SM2-OUT CH11 -15V...
  • Page 45 PINOUT FOR AIO BOARD PIN # SIGNAL NAME IORO- TP13 TP12...
  • Page 46 TP11 TP10 TP18 TP17 TP16...
  • Page 47 TP15 TP14...

  • Page 48: Supplementary Information

    9.1 Introduction The following section contains iistinqs and references to Operation of the analog board in a 9.2 Li?t of Supplementary Information Burr-Brown Application Note AN-79 Burr-Brown Product Specification ADC 80 Burr-Brown Product Specification DAC 80 Zilog Interrupt Structure Application Note...

This manual is also suitable for:

Z80-aib

Table of Contents