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Z8018x
Family MPU User Manual
226
Table 43.
Block Transfer (Continued)
Operation
Name
Mnemonics Op Code
CPI
CPIR
LDD
LDDR
LDI
LDIR
(2) P/V = 0: BC
-1 = 0
R
P/V = 1: BC
R
(3) Z = 1: Ar = (HL)
M
Z = 0 :Ar ≠ (HL)
UM005004-0918
Addressing
Immed Ext Ind Reg RegI Imp Rel
11101101
10100001
11101101
10110001
11 101 101
10 101 000
11 101 101
10 111 000
11 101 101
10 100 000
11 101 101
10 110 000
-1 ≠ 0
M
Bytes States
S
S
2
12
S
S
2
14
12
S/D
2
12
S/D
2
14(BC
R
12(BC
R
S/D
2
12
S/D
2
14(BC
R
12(BC
R
Operation
Ar-(HL)
M
BC
-1→BC
R
R
HL
+ 1→HL
R
R
BC
≠ 0 Ar*(HL)
R
M
BC
= 0 or Ar = (HL)
R
M
Ar-(HL)
M
Q
BC
-1→BC
R
R
HL
+ 1→HL
R
R
Repeat Q until
Ar = (HL)
or BC
= 0
M
R
→ (DE)
(HL)
M
M
BC
-1→BC
R
R
DE
-1→DE
R
R
HL
-1→HL
R
R
≠ 0)
→ (DE)
(HL)
M
M
BC
-1 → BC
R
R
= 0)
-1 → DE
Q
DE
R
R
HL
-1 → HL
R
R
Repeat Q until
BC
= 0
R
(HL)
→DE)
M
R
BC
-1→BC
R
R
DE
+ 1→DE
R
R
HL
+ 1→HL
R
R
≠0)
(HL)
→(DE)
M
M
Q
BC
-1→BC
R
R
= 0)
DE
+ 1→DE
R
R
HL
+ 1→HL
R
R
Repeat Q until
BC
= 0
R
Flags
7 6
4 2
1 0
S Z
H P/V N C
↑ ↑
↑ ↑
S •
(3)
(2)
↑ ↑
↑ ↑
S •
(2)
• •
R ↑
R •
• •
R •
R R
(2)
• •
R ↑
R •
• •
R R
R •
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Do you have a question about the Z8018 Series and is the answer not in the manual?
Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated