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Z8018x
Family MPU User Manual
175
TST (HL) - Test Memory
The contents of memory pointed to by HL are ANDed with the accumulator
(A) and the status flags are updated. The memory contents and accumulator
are not changed (non-destructive AND).
INO g, (m) - Input, Immediate I/O address
The contents of immediately specified 8-bit I/O address are input into the
specified register. When I/O is accessed,
is output in high-order bits
00H
of the address automatically.
OUTO (m), g - Output, Immediate I/O address
The contents of the specified register are output to the immediately
specified 8-bit I/O address. When I/O is accessed, 00H is output in high-
order bits of the address automatically.
CPU REGISTERS
The Z80180 CPU registers consist of Register Set GR, Register Set GR'
and Special Registers.
The Register Set GR consists of 8-bit Accumulator (A), 8-bit Flag Register
(F), and three General Purpose Registers (BC, DE, and HL) which may be
treated as 16-bit registers (BC, DE, and HL) or as individual 8-bit registers
(B, C, D, E, H, and L) depending on the instruction to be executed. The
Register Set GR' is alternate register set of Register Set GR and also contains
Accumulator (A'), Flag Register (F') and three General Purpose Registers
(BC', DE', and HL'). While the alternate Register Set GR' contents are not
directly accessible, the contents can be programmably exchanged at high
speed with those of Register Set GR.
The Special Registers consist of 8-bit Interrupt Vector Register (I), 8-bit R
Counter (R), two 16-bit Index Registers (IX and IY), 16-bit Stack Pointer
(SP), and 16-bit Program Counter (PC)
UM005004-0918
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Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated