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Table 25.
Clock
Frequency
Item
Co
Rs
CL1, CL2
If an external clock input is used instead of a crystal, the waveform (twice
the clock rate) must exhibit a 50% ± 10% duty cycle.
Note:
Figure 70.
Figure 71 illustrates the Z8X180 clock generator circuit while Figures 72
and 72 specify circuit board design rules.
Z8X180 Operating Frequencies
4MHz
<
7 pF
<
Ω
60
±
10 to 22 pF
10%
The minimum clock input High voltage level is V
external clock input is connected to the EXTAL pin, while the
XTAL pin is left open. Figure 70 depicts the external clock
interface.
3
EXTAL
2
XTAL
Open
External Clock Interface
Family MPU User Manual
<
≤
4MHz
f
12MHz 12MHz
<
7 pF
<
Ω
60
±
10 to 22 pF
10%
External Clock Input
Z8018x
<
≤
f
33MHz
<
7 pF
<
Ω
60
±
10 to 22 pF
10%
–0.6V. The
CC
UM005004-0918
169
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Do you have a question about the Z8018 Series and is the answer not in the manual?
Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated