1. Manuals
  2. Brands
  3. ZiLOG Manuals
  4. Computer Hardware
  5. eZ8
  6. User manual

ZiLOG eZ8 User Manual

Hide thumbs Also See for eZ8:
Table of Contents

Advertisement

Quick Links

Download this manual
eZ8 CPU
User Manual
UM012811-0904
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 •
www.ZiLOG.com
Downloaded from
Elcodis.com
electronic components distributor

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the eZ8 and is the answer not in the manual?

Questions and answers

Related Manuals for ZiLOG eZ8

Summary of Contents for ZiLOG eZ8

  • Page 1 CPU User Manual UM012811-0904 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com Downloaded from Elcodis.com electronic components distributor...
  • Page 2 Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded.

  • Page 3: Table Of Contents

    Relocation of the eZ8 CPU Control Registers ....... . 12...
  • Page 4 CPU Instruction Set Description ........

  • Page 5: List Of Figures

    CPU Block Diagram ........
  • Page 6 Table 20. eZ8 CPU Instruction Summary ........

  • Page 7: Manual Objectives

    Manual Organization The User Manual is divided into ten sections; each section details a specific topic about the product. Architectural Overview Presents an overview of the eZ8 CPU’s features and benefits, and a description of its architecture. Z8 Compatibility ®...
  • Page 8 Immediate Data (IM) • Extended Register (ER) Interrupts Describes eZ8 CPU operation in response to interrupt requests from either internal periph- erals or external devices. Illegal Instruction Traps Describes the consequences of executing undefined opcodes. eZ8 CPU Instruction Set Summary Lists assembly language instructions, including mnemonic definitions and a summary of the User Manual instruction set.
  • Page 9 CPU User Manual Where the use of the font is not indicated, as in the Index, the name of the entity is pre- sented in upper case. • Example: FLAGS[1] is smrf Hexadecimal Values Hexadecimal values are designated by uppercase and appear in the typeface.
  • Page 10 It is important that all users understand the following safety terms, which are defined here. Indicates a procedure or file may become corrupted if the Caution: user does not follow directions. Trademarks ® eZ8 and Z8 are trademarks of ZiLOG, Inc. UM012811-0904 Manual Objectives Downloaded from Elcodis.com...

  • Page 11: Architectural Overview

    User Manual Architectural Overview FEATURES The eZ8 is ZiLOG’s latest 8-bit central processing unit (CPU) designed to meet the con- tinuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU exe- ® cutes a superset of the original Z8 instruction set.

  • Page 12: Fetch Unit

    CPU. INSTRUCTION STATE MACHINE The Instruction State Machine is the controller for the eZ8 CPU Execution Unit. After the initial operation decode by the Fetch Unit, the Instruction State Machine takes over and completes the instruction. The Instruction State Machine performs register read and write operations and generates addresses.

  • Page 13: Program Counter

    • Flags The eZ8 CPU register bus can access up to 4K (4096) bytes of register space. In all eZ8 CPU products, the upper 256 bytes are reserved for control of the eZ8 CPU, the on-chip peripherals, and the I/O ports. The eZ8 CPU control registers are always located at addresses from as listed in Table 1 on page 4.

  • Page 14: Table 1. Ez8 Cpu Control Registers

    Stack Pointer High Byte Stack Pointer Low Byte Stack Pointer Registers The eZ8 CPU allows the user to relocate the stack within the Register File. The stack can be located at addresses from . The 12-bit Stack Pointer value is given by...

  • Page 15: Figure 2. Flags Register

    The Sign (S) flag stores the value of the most-significant bit of a result following an arith- metic, logical, rotate or shift operation. For signed numbers, the eZ8 CPU uses binary two’s complement to represent the data and perform the arithmetic operations. A 0 in the...
  • Page 16 CPU User Manual most significant bit position (Bit 7) identifies a positive number; therefore, the Sign flag is also 0. A 1 in the most significant position (Bit 7) identifies a negative number; therefore, the Sign flag is also 1.

  • Page 17: Table 2. Condition Codes

    Byte Ordering For multi-byte data, the eZ8 CPU stores the most significant byte in the lowest memory address. For example, the value 1 can be stored as a 2-byte (16-bit) number in Register...
  • Page 18 CPU User Manual Pair . The value is stored as . The most-significant byte ( ) is 122H 123H 0001H stored in the lowest memory address at . The least-significant byte ( ) is stored in 122H the higher memory address at .

  • Page 19: Z8 Compatibility

    ® Dog Timer Enable During HALT Mode at opcode 4FH). Users with existing Z8 assem- bly code can easily compile their code to use the eZ8 CPU. The assembler for the eZ8 CPU is available for download from www.zilog.com. NEW INSTRUCTIONS The eZ8 CPU features many new instructions to increase processor efficiency and allow access to the expanded 4KB Register File.

  • Page 20: Table 4. New Extended Addressing Instructions

    CPU User Manual Table 3. New Function Instructions (Continued) Mnemonic Instruction Description Bit Test and Jump BTJNZ Bit Test and Jump if Non-Zero BTJZ Bit Test and Jump if Zero Compare with Carry Load Constant LDCI Load Constant and Auto-Increment Addresses...

  • Page 21: Table 5. Instructions With New Opcodes

    . The assembler for the eZ8 CPU continues to support these instructions. Refer to the Address Modes chapter and the LD instruction description for more information. The WDH (Watch-Dog Timer Enable During HALT Mode) instruction has also been removed.

  • Page 22: Relocation Of The Ez8 Cpu Control Registers

    CPU User Manual RELOCATION OF THE EZ8 CPU CONTROL REGISTERS The four control registers within the eZ8 CPU have new addresses to take advantage of the larger Register File. Stack Pointer High and Low Byte Registers The Stack Pointer Low Byte (SPL) now resides at address in the Register File.

  • Page 23: Address Space

    File. The Register File is composed of two sections - control registers and general-purpose registers. The upper 256 bytes are reserved for control of the eZ8 CPU, the on-chip periph- erals, and the I/O ports. These 256 registers are always located at addresses from...

  • Page 24: Table 6. Ez8 Cpu Control Registers

    CPU User Manual Table 6. eZ8 CPU Control Registers Register Address Mnemonic Register Description (Hex) FLAGS Flags Register Pointer Stack Pointer High Byte Stack Pointer Low Byte General-Purpose Registers Other than the upper 256 registers reserved for control functions, all other available addresses within the Register File are available for general-purpose use.

  • Page 25: Figure 3. Register File Organization

    Figure 3. Register File Organization Linear Addressing of the Register File Using 12-bit linear addressing, the eZ8 CPU can directly access any 8-bit registers or 16- bit register pairs within the 4096B Register File. The instructions that support 12-bit addressing allow direct register access to most registers without requiring a change to the value of the Register Pointer (RP).

  • Page 26: Figure 4. Working Register Addressing Example

    The Working Registers within each Working Register Group are accessible using 4-bit addressing. The high nibble of the eZ8 CPU Register Pointer (RP) contains the base address of the active Working Register Group, referred to as the Working Group Pointer.

  • Page 27: Program Memory

    = Even Address Figure 5. 16-Bit Register Pair Addressing Bit Addressing Many eZ8 CPU instructions allow access to individual bits within registers. Figure 6 illus- trates how the instruction AND R15, MASK can clear an individual bit. MASK = DFH AND R15, DFH ;...

  • Page 28: Data Memory

    DATA MEMORY In addition to the Register File and the Program Memory, the eZ8 CPU also accesses a maximum of 64KB (65,536 bytes) of Data Memory. The Data Memory space provides data storage only. Opcode and operand fetches cannot be executed out of this space.

  • Page 29: Figure 7. Stack Operations

    CPU User Manual rupt routines, the Stack Pointer must be set to prepare for possible Illegal Instruction Traps. The stack address decrements prior to a PUSH operation and increments after a POP oper- ation. The stack address always points to the data stored at the top of the stack. The stack is a return stack for interrupts and CALL and TRAP instructions.

  • Page 30: Addressing Modes

    CPU User Manual Addressing Modes INTRODUCTION The eZ8 CPU provides six addressing modes: • Register (R) • Indirect Register (IR) • Indexed (X) • Direct (DA) • Relative (RA) • Immediate Data (IM) With the exception of immediate data and condition codes, all operands are expressed as either Register File, Program Memory, or Data Memory addresses.

  • Page 31: Figure 8. Register Addressing Using 12-Bit Addresses

    CPU User Manual Program Memory Register File 12-bit address is dst[11:0] Destination dst[7:0] Register Two 12-bit {src[3:0}, Addresses dst[11:8]} (dst, src) src[11:4] Three Operand Instruction Opcode (Example) 12-bit address is src[11:0] Source Register Figure 8. Register Addressing Using 12-Bit Addresses...

  • Page 32: Figure 9. Register Addressing Using 8-Bit Addresses

    CPU User Manual Program Memory Register File 12-bit address is {RP[3:0], dst[7:0]} One 8-bit Destination Address dst[7:0] Register (dst) One Operand Opcode Instruction (Example) Figure 9. Register Addressing Using 8-Bit Addresses Register Addressing Using 4-Bit Addresses Working Registers or Working Register Pairs may be accessed using 4-bit addresses sup- plied in the operands.

  • Page 33: Figure 10. Register Addressing Using 4-Bit Addresses

    CPU User Manual Program Memory Register File 12-bit address is {RP[3:0], RP[7:4], dst[3:0]} Two 4-bit {dst[3:0], Destination Addresses src[3:0]} Register (dst, src) One Operand Opcode Instruction (Example) 12-bit address is {RP[3:0], RP[7:4], src[3:0]} Source Register Figure 10. Register Addressing Using 4-Bit Addresses...

  • Page 34: Indirect Register Addressing (Ir)

    CPU User Manual INDIRECT REGISTER ADDRESSING (IR) In Indirect Register Addressing Mode, the contents of the specified Register provide an address as illustrated in Figures 11 and 12. Depending upon the instruction selected, the specified Register contents point to a Register File, Program Memory, or an Data Memory location.

  • Page 35: Indexed Addressing (X)

    CPU User Manual Program Memory Register File Register Pair Destination contains two Register LSB 12-bit address is 8-bit address {RP[3:0], dst[7:0]} One 8-bit {addr[15:8], addr[7:0]} Destination Address dst[7:0] Register MSB (dst) One Operand Opcode Instruction (Example) Program or Data Memory...

  • Page 36: Direct Addressing (Da)

    CPU User Manual Program Memory Register File 12-bit address is {RP[3:0], RP[7:4], dst[3:0]} Destination Index Register Two 4-bit {dst[3:0], Source Address src[3:0]} Register (dst, src) Two Operand Source Opcode Instruction Value (Example) Value used in execution 12-bit address is {RP[3:0], Source Value + Index} Figure 13.

  • Page 37: Relative Addressing (Ra)

    CPU User Manual Program Memory DA[7:0] 16-bit Direct DA[15:0] written to Address Program Counter DA[15:8] Two Operand Instruction Opcode (Example) 16-bit Program Next Memory address Opcode is DA[15:0] Figure 14. Direct Addressing RELATIVE ADDRESSING (RA) Figure 15 illustrates the Relative Addressing mode. The instruction specifies a two’s com- plement signed displacement in the range of –128 to +127.

  • Page 38: Immediate Data Addressing (Im)

    CPU User Manual Program Memory 16-bit Program Next Opcode PC[15:0] Memory address if no Jump is PC[15:0] 8-bit Value If Jump taken, Displacement -128 to +127 PC[15:0] = PC[15:0] + d[7:0] One Operand Instruction Opcode (Example) 16-bit Program Next Opcode...

  • Page 39: Figure 16. Immediate Data Addressing

    CPU User Manual Program Memory Register File 8-bit data written to Destination Immediate Data Destination Register 12-bit address is Two Operand {RP[3:0], dst[7:0]} Instruction Opcode (Example) Figure 16. Immediate Data Addressing UM012811-0904 Addressing Modes Downloaded from Elcodis.com electronic components distributor...

  • Page 40: Interrupts

    Specification for information on the Interrupt Controller. VECTORED INTERRUPT PROCESSING Each eZ8 CPU interrupt is assigned its own vector. When an interrupt occurs, control passes to the interrupt service routine pointed to by the interrupt’s vector location in Pro- gram Memory. The sequence of events for a vectored interrupt is as follows:...

  • Page 41: Figure 17. Effects Of An Interrupt On The Stack

    CPU User Manual 1. Push the low byte of the Program Counter, PC[7:0], on the stack. 2. Push the high byte of the Program Counter, PC[15:8], on the stack. 3. Push the Flags Register on the stack. 4. Fetch the High Byte of the Interrupt Vector 5.

  • Page 42: Nesting Of Vectored Interrupts

    CPU User Manual Program Memory Program Memory Address Interrupt Service 4567H Routine Origin Interrupt Vector 0015H Vector[7:0] = 67H Table Vector Selected by 0014H Vector[15:8] = 45H Interrupt Controller Figure 18. Interrupt Vectoring in Program Memory Example NESTING OF VECTORED INTERRUPTS Vectored interrupt nesting allows higher priority requests to interrupt a lower priority request.

  • Page 43: Polled Interrupt Processing

    The eZ8 CPU generates Software Interrupts by writing to the Interrupt Request Registers in the Register File. The Interrupt Controller and eZ8 CPU handle these software inter- rupts in the same manner as hardware-generated interrupt requests. To generate a Software Interrupt, write a 1 to the desired interrupt request bit in the selected Interrupt Request Register.

  • Page 44: Illegal Instruction Traps

    Illegal Instruction Traps Description The instruction set of the eZ8 CPU does not cover all possible sequences of binary values. Binary values and sequences for which no operation is defined are illegal instructions. When the eZ8 CPU fetches one of these illegal instructions, it performs an Illegal Instruc- tion Trap operation.

  • Page 45: Ez8 Cpu Instruction Set Summary

    The assembler processes the source program to obtain a machine language program called the object code. The eZ8 CPU executes the object code. An example segment of an assem- bly language program is detailed in the following example. Assembly Language Source Program Example ;...

  • Page 46: Assembly Language Syntax

    234H ASSEMBLY LANGUAGE SYNTAX For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as ‘destination, source’. After assembly, the object code usually places the operands in the order ’source, destination’, but ordering is opcode-dependent. The fol- lowing instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler.

  • Page 47: Table 10. Notational Shorthand

    Index value (#Index) in a +127 to -128 range. Table 11 contains additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections. UM012811-0904 eZ8 CPU Instruction Set Summary Downloaded from Elcodis.com electronic components distributor...

  • Page 48: Ez8 Cpu Instruction Classes

    + src indicates the source data is added to the destination data and the result is stored in the des- tination location. EZ8 CPU INSTRUCTION CLASSES eZ8 CPU instructions can be divided functionally into the following groups: • Arithmetic •...

  • Page 49: Table 12. Arithmetic Instructions

    Subtract using Extended Addressing Table 13. Bit Manipulation Instructions Mnemonic Operands Instruction BCLR bit, dst Bit Clear p, bit, dst Bit Set or Clear BSET bit, dst Bit Set UM012811-0904 eZ8 CPU Instruction Set Summary Downloaded from Elcodis.com electronic components distributor...

  • Page 50: Table 14. Block Transfer Instructions

    Enable Interrupts HALT — Halt Mode — No Operation — Reset Carry Flag — Set Carry Flag Set Register Pointer STOP — Stop Mode — Watch-Dog Timer Refresh UM012811-0904 eZ8 CPU Instruction Set Summary Downloaded from Elcodis.com electronic components distributor...

  • Page 51: Table 16. Logical Instructions

    Logical AND using Extended Addressing Complement dst, src Logical OR dst, src Logical OR using Extended Addressing dst, src Logical Exclusive OR XORX dst, src Logical Exclusive OR using Extended Addressing UM012811-0904 eZ8 CPU Instruction Set Summary Downloaded from Elcodis.com electronic components distributor...

  • Page 52: Table 18. Program Control Instructions

    Table 19. Rotate and Shift Instructions Mnemonic Operands Instruction BSWAP Bit Swap Rotate Left Rotate Left through Carry Rotate Right Rotate Right through Carry Shift Right Arithmetic Shift Right Logical SWAP Swap Nibbles UM012811-0904 eZ8 CPU Instruction Set Summary Downloaded from Elcodis.com electronic components distributor...

  • Page 53: Ez8 Cpu Instruction Summary

    User Manual EZ8 CPU INSTRUCTION SUMMARY Table 20 summarizes the eZ8 CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch, and the number of CPU clock cycles required for the instruction execution.
  • Page 54 CPU User Manual Table 20. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Opcode(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← dst AND src AND dst, src dst ← dst AND src...
  • Page 55 CPU User Manual Table 20. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Opcode(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← 00H CLR dst dst ← ~dst COM dst...
  • Page 56 CPU User Manual Table 20. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Opcode(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← dst - 1 DECW dst Disable Interrupts IRQCTL[7] ← 0 dst ←...
  • Page 57 CPU User Manual Table 20. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Opcode(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← src LD dst, src 0C-FC X(r) X(r) dst ← src LDC dst, src dst ←...
  • Page 58 CPU User Manual Table 20. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Opcode(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← src LDX dst, src X(rr) X(rr) dst ← src + X...
  • Page 59 CPU User Manual Table 20. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Opcode(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← @SP POP dst SP ← SP + 1 dst ←...
  • Page 60 CPU User Manual Table 20. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Opcode(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← dst – src - C SBC dst, src dst ←...
  • Page 61 CPU User Manual Table 20. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Opcode(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst[7:4] ↔ dst[3:0] SWAP dst TCM dst, src (NOT dst) AND src...
  • Page 62 CPU User Manual Table 20. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Opcode(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← dst XOR src XOR dst, src dst ← dst XOR src...

  • Page 63: Ez8 Cpu Instruction Set Description

    User Manual eZ8 CPU Instruction Set Description The following pages provide detailed descriptions of the assembly language instructions available with the eZ8 CPU. The instruction set available with the eZ8 CPU is a superset ® of the original Z8 instruction set. The instruction set descriptions on the following pages are organized alphabetically by mnemonic.
  • Page 64 Set if the result is negative; reset otherwise. Set if an arithmetic overflow occurs; reset otherwise. Reset to 0. Set if there is a carry from bit 3 of the result; reset otherwise. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 65 ADC 34H, 12H Object Code: 14 12 34 leaves the value in Register 34H, sets the H flag and clears the C, Z, S, V, and D flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 66 Carry flag is set, the statement: ADC @D4H, #02H Object Code: 17 D4 02 leaves the value in Register 5FH and clears the C, Z, S, V, D, and H flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 67 {RP[3:0], RP[7:4], 3H}. To access Registers on Page EH (addresses ), set the Page Pointer, RP[3:0], E00H EFFH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 68 , and the Carry flag is not set, the statement: ADCX 46CH, #03H Object Code: 19 03 04 6C leaves the value in Register 46CH and clears the C, Z, S, V, D, and H flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 69 ) is the desired destination operand, as the destination operand in the opcode. To access Registers with addresses to E , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 70 Register 5FH contains the value , the statement: ADD @D4H, #02H Object Code: 07 D4 02 leaves the value in Register 5FH and clears C, Z, S, V, D, and H flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 71 To access Registers on Page EH (addresses ), set the Page Pointer, RP[3:0], E00H EFFH to EH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 72 ADDX 46CH, #03H Object Code: 09 03 04 6C leaves the value 2DH in Register 46CH and clears the C, Z, S, V, D, and H flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 73 ) is the desired destination operand, as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 74 • Using Escaped Mode Addressing, if Working Register R3 contains the value Register 3EH contains the value (11101100B), the statement: AND @R3, #05H Object Code: 57 E3 05 UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 75 CPU User Manual leaves the value (00000100B) in Register 3EH and clears the Z, V, and S flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 76 {RP[3:0], RP[7:4], 3H}. To access Registers on Page EH (addresses E00H to EFFH), set the Page Pointer, RP[3:0], and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 77 (11110111B), the statement: ANDX D7AH, #F0H Object Code: 59 F0 0D 7A leaves the value (11110000B) in Register 7AH, sets the S flag and clears the Z and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 78 Blocks all interrupt and DMA requests during execution of the next 3instructions. Description The Atomic instruction forces the eZ8 CPU to execute the next 3 instructions as a single block (i.e. atom) of operations. During execution of these next 3 instructions, all interrupts and DMA requests are prevented.
  • Page 79 If Working Register R7 contains the value (00111000B), the statement: BCLR 4, R7 Object Code: E2 47 leaves the value (00101000B) in Working Register R7 and clears the V flag. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 80 If Working Register R7 contains the value (00111000B), the statement: BIT 1, 2, R7 Object Code: E2 A7 leaves the value (00111010B) in Working Register R7 and clears the V flag. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 81 Specification for information regarding the on-chip debugger. Flags Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Attributes Mnemonic Destination, Source Opcode (Hex) Operand 1 Operand 2 Operand 3 — — — — UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 82 If Working Register R7 contains the value (00111000B), the statement: BSET 2, R7 Object Code: E2 A7 leaves the value (00111010B) in Working Register R7 and clears the V flag. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 83 , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. Example • If Register 27H contains the value (01010011B), the statement: BSWAP 27 Object Code: D5 27 UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 84 CPU User Manual leaves the value (11001010B) in Register 27, sets the S flag and clears the V flag.. The C flag is undefined. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...

  • Page 85: Figure 20. Btj Operand Description

    = p { ← PC + X where the jump offset, X, is calculated by the eZ8 CPU assembler from the Program Counter (PC) value and the Destination Address (DA). Description The selected bit in the source operand or register pointed to by the source operand is com- pared with the p flag bit.
  • Page 86 If Working Register R7 contains the value (00100000B), the BTJ instruction that begins the following code segment: Assembly Code Object Code BTJ 1, 5, r7, NEXT F6 D7 01 HALT UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 87 1. The next instruction executed after the BTJ is the LD instruction. The eZ8 CPU assembler automatically calculates the desired displacement value of allowing the Program Counter to skip the one byte HALT instruction and jump to the NEXT label that identifies the LD instruction address.

  • Page 88: Figure 21. Btjnz Operand Description

    = 1 { ← PC + X where the jump offset, X, is calculated by the eZ8 CPU assembler from the Program Counter (PC) value and the Destination Address (DA). Description The selected bit in the source operand or register pointed to by the source operand is com- pared with the a logical 1.
  • Page 89 1. The next instruction executed after the BTJNZ is the LD instruction. The eZ8 CPU assembler automatically calculates the desired displacement value of , allowing the Program Counter to skip the one byte HALT instruction and jump to the NEXT label that identifies the LD instruction address.
  • Page 90 Program Counter jump to occur because bit 3 of Working Register R7 fails the test for a 1. The next instruction executed after the BTJNZ is the HALT instruction. The flags are unaffected. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...

  • Page 91: Figure 22. Btjz Operand Description

    = 0 { ← PC + X where the jump offset, X, is calculated by the eZ8 CPU assembler from the Program Counter (PC) value and the Destination Address (DA). Description The selected bit in the source operand or register pointed to by the source operand is com- pared with a logical 0.
  • Page 92 NEXT label that identifies the LD instruction address. The flags are unaffected. • If Working Register R7 contains the value (00100000B), the BTJZ instruction that begins the following code segment: UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 93 Program Counter jump to occur because bit 5 of Working Register R7 fails the test for a 0. The next instruction executed after the BTJZ is the HALT instruction. The flags are unaffected. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 94 ) is the desired destination operand, use as the desti- nation operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 95 Program Counter with . The Program Counter now points to the address of the 3521H first statement in the called procedure to be executed. The flags are unaffected. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 96 Operand 1 Operand 2 Operand 3 — — — — Example If the Carry flag contains a 0, the statement: Object Code: EF sets the Carry flag to 1. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 97 Examples • Using Escaped Mode Addressing, if Working Register R6 contains , the statement: CLR R6 Object Code: B0 E6 leaves the value in Working Register R6. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 98 If Register A5H contains the value , and Register 23H contains the value , the statement: CLR @A5H Object Code: B1 A5 leaves the value in Register 23H. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 99 If Register 08H contains (00100100B), the statement: COM 08H Object Code: 60 08 leaves the value (11011011B) in Register 08H, sets the S flag and clears the Z and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 100 (11111111B), the statement: COM @08H Object Code: 61 08 leaves the value (00000000B) in Register 24H, sets the Z flag is set and clears the V and S flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 101 ) is the desired destination operand, as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 102 , and Register FCH contains the value , the statement: CP @D4H, #FFH Object Code: A7 D4 FF sets the V flag, and clears the C, Z, and S flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 103 ) is the desired destination operand, as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing.S UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 104 , and the Carry Flag is 0, the statement: CPC @D4H, #FFH Object Code: 1F A7 D4 FF sets the V flag, and clears the C, Z, and S flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 105 {RP[3:0], RP[7:4], 3H}. To access Registers on Page EH (addresses ), set the Page Pointer, RP[3:0], E00H EFFH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 106 , the Carry flag is 0, and the Zero flag is 0, the statement: CPCX 26CH, #2AH Object Code: 1F A9 2A 02 6C sets the Z flag and clears the C, S, and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 107 To access Registers on Page EH (addresses E00H to EFFH), set the Page Pointer, RP[3:0], to EH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 108 • If Register 2 contains , the statement: CPX 26CH, #2AH Object Code: A9 6C 2A sets the Z flag and clears the C, S, and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...

  • Page 109: Table 21. Operation Of The Daa Instruction

    Table 21. Operation of the DAA Instruction Carry Bits 7-4 H Flag Bits 3-0 Number Carry Instruction Before Value Before Value Added To After (HEX) (HEX) Byte ADD\ADC SUB\SBC UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 110 0011 1100 = 3CH 0000 0110 = 06H 0100 0010 = 42H Register 5F contains the value and clears the C, Z, and S flags. V is undefined. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 111 Working Register R10 and clears the Z, V, and S flags. • If Register B3H contains CBH, and Register CBH contains , the statement: UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 112 CPU User Manual DEC @B3H Object Code: 31 B3 leaves the value in Register CBH, sets the Z flag and clears the V and S flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 113 ECH as the destination operand in the opcode. To access Register Pairs with addresses E0H to EFH, either set the Working Group Pointer, RP[7:4], to EH or use indirect address- ing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 114 FAF3H DECW @R0 Object Code: 81 E0 leaves the value in Register Pair 30H and 31H, sets the S flag and clears the. Z FAF2H and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 115 (10000000B), interrupts are globally enabled. Upon execution of the DI command, the statement: Object Code: 8FH the IRQCTL (Interrupt Control register FCFH) contains (00000000B) and globally disables interrupts. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 116 ← PC + X where the jump offset, X, is calculated by the eZ8 CPU assembler from the Program Counter (PC) value and the Destination Address (DA). Description The Working Register that is used as a counter is decremented. If the contents of the...
  • Page 117 1. Load the R6 counter with 18d (12H). 2. Load the R4 source pointer. 3. Load the R2 destination pointer. 4. Set up the loop to perform moves. 5. End loop with DJNZ. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 118 ;Load byte in R3 from source Ld @R2, R3 ;Write byte to destination dec R4 ;Decrement source pointer dec R2 ;Decrement destination pointer djnz R6, loop ;Decrement and loop until count = 0 UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 119 Upon execution of the EI command, the statement: Object Code: 9FH the IRQCTL (Interrupt Control register FCFH) contains the value (10000000B) and globally enable interrupts. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 120 CPU User Manual HALT Halt Mode HALT Operation Halt Mode Description The HALT instruction places the eZ8 CPU into HALT mode. Refer to the device-specific Product Specification for information on HALT mode operation. Flags Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
  • Page 121 Set if the result is zero; reset otherwise. Set if Bit 7 of the result is set; reset otherwise. Set if an arithmetic overflow occurs; reset otherwise. Unaffected. Unaffected. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 122 ) is the desired destination operand, use as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 123 Register CBH contains , the statement: INC @B3H Object Code: 21 B3 leaves the value in Register CBH, sets the Z flag and clears the V and S flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 124 ECH as the destination operand in the opcode. To access Register Pairs with addresses E0H to EFH, either set the Working Group Pointer, RP[7:4], to EH or use indirect address- ing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 125 FAF3H INCW @R0 Object Code: A1 E0 leaves the value in Register Pair 30H and 31H, sets the S flag and clears the Z FAF4H and V flag. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 126 Stack Pointer Low to the value . The Stack Pointer High register remains unchanged with the value . The next instruction to be executed is at 6FE4H. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 127 , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. Example • If Working Register Pair RR2 contains the value , the statement: 3F45H JP @RR2 Object Code: C4 E2 UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 128 CPU User Manual replaces the contents of the PC with the value and transfers program control to 3F45H that location. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 129 Otherwise, the instruction following the JP instruction is executed. for more information. Section Condition Codes <Plain>on page 6 Flags Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 130 Program Counter with the value and transfers 1520H program control to that location. If the Carry flag was not set, control would have passed through to the statement following the JP instruction. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 131 Operation ← PC + X where the jump offset, X, is calculated by the eZ8 CPU assembler from the Program Counter (PC) value and the Destination Address (DA). Description The relative address offset is added to the Program Counter and control passes to the instruction located at the address specified by the Program Counter.
  • Page 132 If cc (condition code) is true (1){ ← PC + X where the jump offset, X, is calculated by the eZ8 CPU assembler from the Program Counter (PC) value and the Destination Address (DA). Description If the condition specified by the “cc” is true, the relative address offset is added to the Pro- gram Counter and control passes to the instruction located at the address specified by the Program Counter.
  • Page 133 GE, DA — — GT, DA — — UGT, DA — — NOV, DA — — PL, DA — — NE, DA — — NC, DA — — UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 134 Description The contents of the source operand are loaded into the destination operand. The contents of the source operand are unaffected. Flags Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 135 ) is the desired destination operand, as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 136 Register 34H. The contents of Register 45H are not affected. • If Register 45H contains the value and Register CFH contains the value , the statement: LD 34H, @45H Object Code: E5 45 34 UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 137 Object Code: D7 A0 F0 loads the value into Register FBH (F0H + 0BH = FBH). The contents of Working Registers R0 and R10 are unaffected by the load. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 138 If Working Register R2 contains the value , and Working Register Pair R6 and R7 contains the value , the statement: 10A2H LDC @RR6, R2 Object Code: D2 26 UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 139 CPU User Manual loads the value 22H into Program Memory location 10A2H. The value of Working Register R2 is unchanged by the load. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 140 Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Attributes Mnemonic Destination, Source Opcode (Hex) Operand 1 Operand 2 Operand 3 LDCI @r1, @rr2 {r1, rr2} LDCI @rr1, @r2 {r2, rr1} UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 141 LDCI @RR6, @R2 Object Code: D3 26 loads the value into Program Memory location 30A3H. Working Register R2 increments to 22H and Working Register Pair R6-R7 increments to 30A4H. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 142 If Working Register Pair R6 and R7 contain the value and Working Register 404AH R2 contains the value , the statement: LDE @RR6, R2 Object Code: 92 26 loads the value into Data Memory location 404AH. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 143 Unaffected. Unaffected. Attributes Mnemonic Destination, Source Opcode (Hex) Operand 1 Operand 2 Operand 3 LDEI @r1, @rr2 {r1, rr2} — — LDEI @rr1, @r2 {r2, rr1} — — UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 144 LDEI @RR6, @R2 Object Code: 93 26 loads the value into Data Memory location 404BH. Working Register R2 increments to 24H and Working Register Pair RR6 increments to 404CH. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 145 {RP[3:0], RP[7:4], 2H}. To access Registers on Page EH (addresses ), set the Page Pointer, RP[3:0], E00H EFFH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 146 ER1, r2 {r2, ER1[11:8]} ER1[7:0] — ER1, @r2 {r2, ER1[11:8]} ER1[7:0] — @RR1, R2 — @.ER(RR1), @R2 — ER1, ER2 ER2[11:4] {ER2[3:0], ER1[11:8]} ER1[7:0] ER1, IM {0H, ER1[11:8]} ER1[7:0] UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 147 {RP[3:0], RP[7:4], 3H}. To access Registers on Page EH (addresses ), set the Page Pointer, RP[3:0], E00H EFFH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 148 Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Attributes Mnemonic Dest, Src, d Opcode (Hex) Operand 1 Operand 2 Operand 3 r1, X(r2) {r1, r2} — rr1, X(rr2) {rr1, rr2} — UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 149 16-bit result of 2324H in Working Register Pair RR12, stores the most significant byte value in Working Register R12 and stores the least significant byte value in Working Register R13. The flags are unaffected. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 150 Example • Using Escaped Mode Addressing, if Working Register R4 contains the value Working Register R5 contains the value , the statement: MULT E4H Object Code: F4 E4 UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 151 , stores the most significant byte of the result ( ) in Working 2B72H Register R4 and stores the least significant byte of the result ( ) in Working Register R5. The flags are unaffected. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 152 No action is performed by this instruction. It is typically used as a cycle timing delay. Flags Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Attributes Mnemonic Destination, Source Opcode (Hex) Operand 1 Operand 2 Operand 3 — — — — UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 153 ) is the desired destination operand, as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 154 Register 3EH contains the value (00001100B), the statement: OR @R3, #05H Object Code: 47 E3 05 leaves the value (00001101B) in Register 3EH and clears the Z, V, and S flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 155 {RP[3:0], RP[7:4], 3H}. To access Registers on Page (addresses ), set the Page Pointer, RP[3:0], E00H EFFH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 156 If Register D7AH contains the value (00000111B), the statement: ORX D7AH, #01100000B Object Code: 49 60 0D 7A leaves the value (01100111B) in Register D7AHand clears the S, Z and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 157 ) is the desired destination operand, use as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 158 Object Code: 51 E6 loads the value into Register 22H. After the POP operation, the Stack Pointer contains the value . The contents of Working Register R6 are not affected. 0081H UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 159 {RP[3:0], RP[7:4], 3H}. To access Registers on Page EH (addresses ), set the Page Pointer, RP[3:0], E00H EFFH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 160 Object Code: D8 34 50 loads the value into Register 345H. After the POP operation, the Stack Pointer contains the value . The contents of Register D70H are not affected. D71H UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 161 ) is the desired source operand, use as the source operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 162 If the Stack Pointer contains the value the statement: D20H, PUSH #FCH Object Code: 1F70FC Stores the value FCH in location D1FH. After the PUSH operation, the Stack Pointer contains the value D1FH. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 163 To access Registers on Page EH (addresses E00H to EFFH), set the Page Pointer, RP[3:0], to EH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 164 PUSHX FCAH Object Code: C8 FC A0 stores the contents of Register FCAH in location . After the PUSHX operation, D23H the Stack Pointer contains the value D23H UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 165 Operand 1 Operand 2 Operand 3 — — — — Example If the Carry flag is currently set, the statement: Object Code: CF resets the Carry flag to 0. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 166 , the statement: Object Code: AF leaves the value 01A2 in the SP, and the PC contains the value , the address of the 3015H next instruction to be executed. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 167 ) is the desired destination operand, use as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 168 (01000100B), the statement: RL @C6H Object Code: 91 C6 leaves the value in Register 88H (10001000B), sets the S and V flags and clears the C and Z flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 169 ) is the desired destination operand, use as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 170 (10001111B), the statement: RLC @R4 Object Code: 11 E4 leaves Register C6 with the value (00011110B), sets the C and V flags and clears the S and Z flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 171 ) is the desired destination operand, use as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 172 Register 31H contains the value (01111110B), the statement: RR @C6 Object Code: E1 C6 leaves the value (00111111) in Register 31H and clears the C, Z, V, and S flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 173 ) is the desired destination operand, use as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 174 (00000000B) and the Carry flag is reset, the statement: RRC @2CH Object Code: C1 2C leaves the value (00000000B) in Register EDH and resets the C, Z, S, and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 175 This instruction subtracts the source operand and the Carry (C) flag from the destination. The destination stores the result. The contents of the source operand are unaffected. The eZ8 CPU performs subtraction by adding the two’s-complement of the source operand to the destination operand. In multiple-precision arithmetic, this instruction permits the carry (borrow) from the subtraction of low-order operands to be subtracted from the subtraction of high-order operands.
  • Page 176 SBC @D4H, #02H Object Code: 37 D4 02 leaves the value in Register 5FH, sets the D flag and clears the C, Z, S, V and H flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 177 This instruction subtracts the source operand and the Carry (C) flag from the destination. The destination stores the result. The contents of the source are unaffected. The eZ8 CPU performs subtraction by adding the two’s-complement of the source operand to the desti- nation operand.
  • Page 178 Carry flag is not set, the statement: SBCX C6CH, #03H Object Code: 39 03 0C 6C leaves the value in Register C6CH, sets the. D flag and clears the C, Z, S, V and UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 179 Operand 1 Operand 2 Operand 3 — — — — Example If the Carry flag is currently reset, the statement: Object Code: DF sets the Carry flag to 1. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 180 ) is the desired destination operand, use as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 181 (10111000B), the statement: SRA @C6 Object Code: D1 C6 leaves the value (11011100B) in Register DFH, resets the C, Z and V flags and sets the S flag. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 182 ) is the desired destination operand, use as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 183 , and Register DFH contains the value (11111000B), the statement: SRL @C6 Object Code: 1F C1 C6 leaves the value (01111100B) in Register DFH and resets the C, Z, S and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 184 Register File. All references to Working Registers now affect this group of 16 registers. Registers can be accessed as Working Registers R0 to R15. 0F0H 0FFH UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 185 CPU User Manual STOP STOP Mode STOP Operation Stop Mode. Description This instruction places the eZ8 CPU into STOP mode. Refer to the device-specific Product Specification for details of STOP mode operation. Flags Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
  • Page 186 This instruction subtracts the source operand from the destination operand. The destina- tion operand stores the result. The source operand contents are unaffected. The eZ8 CPU performs subtraction by adding the two’s complement of the source operand to the desti- nation operand.
  • Page 187 SUB @D4H, #02H Object Code: 27 D4 02 leaves the value in Register 5FH, sets the D flag and clears the C, Z, S, V and H flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 188 This instruction subtracts the source operand from the destination operand. The destina- tion operand stores the result. The source operand contents are unaffected. The eZ8 CPU performs subtraction by adding the two’s complement of the source operand to the desti- nation operand.
  • Page 189 SUBX 56CH, #03H Object Code: 29 03 05 6C leaves the value in Register 56CH, sets the D flag and clears the C, Z, S, V and H flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 190 ) is the desired destination operand, use as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 191 Register BCH contains the value (10110011B), the statement: SWAP @R5H Object Code: F1 E5 leaves the value (00111011B) in Register BCH and clears the Z and S flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 192 ) is the desired destination operand, use ECH as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 193 1) and clears the S and V flags. • If Register 5DH contains the value , and Register A0H contains the value (00001111B), the statement: TCM @5D, #10H Object Code: 67 5D 10 UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 194 4 of the Register A0H for 1, resets the Z flag (indicating bit 4 in the destination operand was not 1) and clears the S and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 195 {RP[3:0], RP[7:4], 3H}. To access Registers on Page EH (addresses ), set the Page Pointer, RP[3:0], E00H EFFH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 196 1 of the destination operand for 1, sets the Z flag (indicating bit 1 in the destination operand is 1) and clears the S and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 197 ) is the desired destination operand, as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 198 1 of the destination operand for 0, sets the Z flag (indicating bit 1 in the destination operand is 0) and clears the S and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 199 4 of the Register A0H for 0, sets the Z flag (indicating bit 4 in the destination operand was 0) and clears the S and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 200 {RP[3:0], RP[7:4], 3H}. To access Registers on Page EH (addresses E00H to EFFH), set the Page Pointer, RP[3:0], and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 201 1 of the destination operand for 0 sets the Z flag (indicating bit 1 in the destination operand is 0) and clears the S and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 202 This instruction executes a software trap. The Program Counter and Flags are pushed onto the stack. The eZ8 CPU loads the 16-bit Program Counter with the value stored in the Trap Vector Pair. Execution begins from the new value in the Program counter. Execute an IRET instruction to return from a trap.
  • Page 203 CPU User Manual pushes the Flags and Program Counter onto the stack. The Program Counter loads the value . Program execution resumes at address A02FH A02FH UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 204 The first execution of the statement: Object Code: 5F enables the Watch-Dog Timer. • If the Watch-Dog Timer is enabled, the statement: Object Code: 5F refreshes the Watch-Dog Timer. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 205 ) is the desired destination operand, as the destination operand in the opcode. To access Registers with addresses , either set the Working Group Pointer, RP[7:4], to or use indirect addressing. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 206 Register 3EH contains the value (01101100B), the statement: XOR @R3, #05H Object Code: B7 E3 05 leaves the value (01101001B) in Register 3EH and clears the Z, V, and S flags UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 207 {RP[3:0], RP[7:4], 3H}. To access Registers on Page EH (addresses ), set the Page Pointer, RP[3:0], E00H EFFH and set the Working Group Pointer, RP[7:4], to the desired Working Group. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...
  • Page 208 If Register D7AH contains the value (00000111B), the statement: XORX D7AH, #01100110B Object Code: B9 66 0D 7A leaves the value (01100001B) in Register 7AH and clears the S, Z and V flags. UM012811-0904 eZ8 CPU Instruction Set Description Downloaded from Elcodis.com electronic components distributor...

  • Page 209: Opcode Maps

    CPU User Manual Opcode Maps Figure 23 illustrates opcode map cell description and Table 22 explains the abbreviations used in Figure 24 and 25. Opcode Lower Nibble Fetch Cycles Instruction Cycles Opcode Upper Nibble R2,R1 First Operand Second Operand...

  • Page 210: Table 22. Opcode Map Abbreviations

    CPU User Manual Table 22. Opcode Map Abbreviations Abbreviation Description Abbreviation Description Bit position Indirect Register Pair Condition code Polarity (0 or 1) 8-bit signed index or displacement r 4-bit Working Register Destination address 8-bit register Extended Addressing register...
  • Page 211 CPU User Manual Lower Nibble (Hex) ADDX ADDX DJNZ r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1 r1,X cc,X r1,IM cc,DA See 2nd ADCX ADCX Opcode r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1 SUBX SUBX r1,r2 r1,Ir2 R2,R1...
  • Page 212 CPU User Manual Lower Nibble (Hex) PUSH CPCX CPCX r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1 LDWX ER1,ER2 Figure 25. Second Opcode Map after 1FH UM012811-0904 Opcode Maps Downloaded from Elcodis.com electronic components distributor...

  • Page 213: Opcodes Listed Numerically

    User Manual Opcodes Listed Numerically Table 23 lists the eZ8 CPU instructions, sorted numerically by the opcode. The table iden- tifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch, and the number of CPU clock cycles required for the instruction execution.
  • Page 214 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles RLC dst ADC dst, src ADC dst, src ADC dst, src ADC dst, src ADC dst, src...
  • Page 215 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles INC dst INC dst SUB dst, src SUB dst, src SUB dst, src SUB dst, src SUB dst, src...
  • Page 216 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles DJNZ dst, RA JR ULE, dst LD dst, src JP ULE, dst INC dst DA dst DA dst...
  • Page 217 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles AND dst, src AND dst, src ANDX dst, src ANDX dst, src DJNZ dst, RA JR MI, dst...
  • Page 218 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles PUSH src PUSH src TM dst, src TM dst, src TM dst, src TM dst, src TM dst, src...
  • Page 219 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles DJNZ dst, RA JR dst LD dst, src JP dst INC dst RL dst RL dst LDE dst, src...
  • Page 220 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles CP dst, src CP dst, src CP dst, src CP dst, src CPX dst, src CPX dst, src...
  • Page 221 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles INC dst IRET RRC dst RRC dst LDC dst, src LDCI dst, src JP dst LDC dst, src...
  • Page 222 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles JR PL, dst LD dst, src JP PL, dst INC dst RR dst RR dst BIT p, bit, dst...
  • Page 223 CPU User Manual Table 23. eZ8 CPU Instructions Sorted by Opcode Address Mode Flags Opcode(s) Fetch Instr. (Hex) Assembly Mnemonic Cycles Cycles LD dst, src BTJ p, bit, src, dst BTJ p, bit, src, dst DJNZ dst, RA JR NC, dst...

  • Page 224: Assembly And Object Code Example

    User Manual Assembly and Object Code Example Table 24 provides an example listing file output for an assembled eZ8 CPU program. Most of the opcodes appear in this list. The table is sorted alphabetically by the instruction mne- monics. Each instruction line consists of the Program Counter address for the instruction, the object code, and the assembly code (instruction and operands).
  • Page 225 CPU User Manual Table 24. Assembly and Object Code Example (Continued) Program Counter Object Code (Hex) (Hex) Instruction Operand 1 Operand 2 Operand 3 Operand 4 001032 53 68 001034 54 55 34 %34, 001037 55 AA 35 %35,...
  • Page 226 CPU User Manual Table 24. Assembly and Object Code Example (Continued) Program Counter Object Code (Hex) (Hex) Instruction Operand 1 Operand 2 Operand 3 Operand 4 001079 A2 57 00107B A3 68 00107D A4 55 34 %34, 001080 A5 AA 35...
  • Page 227 CPU User Manual Table 24. Assembly and Object Code Example (Continued) Program Counter Object Code (Hex) (Hex) Instruction Operand 1 Operand 2 Operand 3 Operand 4 0010C8 5A F4 DJNZ LABEL2 0010CA 6A F2 DJNZ LABEL2 0010CC 7A F0...
  • Page 228 CPU User Manual Table 24. Assembly and Object Code Example (Continued) Program Counter Object Code (Hex) (Hex) Instruction Operand 1 Operand 2 Operand 3 Operand 4 0010F2 0010F3 0010F4 A0 34 INCW 0010F6 A1 48 INCW @%48 0010F8 IRET...
  • Page 229 CPU User Manual Table 24. Assembly and Object Code Example (Continued) Program Counter Object Code (Hex) (Hex) Instruction Operand 1 Operand 2 Operand 3 Operand 4 00113A 5B 14 LABEL3 00113C 6B 12 LABEL3 00113E 7B 10 LABEL3 001140...
  • Page 230 CPU User Manual Table 24. Assembly and Object Code Example (Continued) Program Counter Object Code (Hex) (Hex) Instruction Operand 1 Operand 2 Operand 3 Operand 4 001173 D7 74 05 %5(r4), 001176 E3 57 001178 E4 55 34 %34,...
  • Page 231 CPU User Manual Table 24. Assembly and Object Code Example (Continued) Program Counter Object Code (Hex) (Hex) Instruction Operand 1 Operand 2 Operand 3 Operand 4 0011C0 E8 45 63 51 %351, %456 0011C4 E9 35 03 64 %364,...
  • Page 232 CPU User Manual Table 24. Assembly and Object Code Example (Continued) Program Counter Object Code (Hex) (Hex) Instruction Operand 1 Operand 2 Operand 3 Operand 4 001207 C1 46 @%46 001209 32 57 00120B 33 68 00120D 34 55 34...
  • Page 233 CPU User Manual Table 24. Assembly and Object Code Example (Continued) Program Counter Object Code (Hex) (Hex) Instruction Operand 1 Operand 2 Operand 3 Operand 4 001252 65 AA 35 %35, @%AA 001255 66 36 31 %36, #%31 001258...

  • Page 234: Index

    11 bit test and jump 75 ALU 1 if zero 81 AND 41, 63 block diagram, eZ8 CPU 2 using extended addressing 41 block transfer instructions 38, 40 ANDX 41, 66, 68 BRK 42 arithmetic instructions 38, 39...
  • Page 235 1 control registers 1, 13 relocation of control registers 12 CPX 39, 97 removed Z8 instructions 11 DA 37, 39, 99 features, eZ8 1 data memory 13, 18 fetch unit 1, 2 DEC 39, 101 FLAGS 38 decimal adjust 99...
  • Page 236 CPU User Manual CLR 41, 87 COM 41, 89 illegal instruction traps 34 complement carry flag 5 IM 37 CP 39, 91 immediate data notation 37 CPC 39, 93 immediate operand prefix symbol 38 CPCX 39, 95 INC 39...
  • Page 237 CPU User Manual POPX 41, 149 priority 30 software interrupt generation 33 program control 38, 42 PUSH 41, 151 vectored processing 30 PUSHX 41, 153 IR 37 RCF 40, 155 Ir 37 IRR 37 reset carry flag 5 Irr 37...
  • Page 238 CPU User Manual using extended addressing 66, 68 operands 35 operations 35 logical exclusive OR 195 OR 41, 143 using extended addressing 197 using extended addressing 41 logical instructions 38 instructions ORX 41, 145 overflow flag 6 logical 41...
  • Page 239 CPU User Manual symbol 38 SRP 40, 174 register notation 37 stack pointer register pair notation 37 compatibility 12 relative address notation 37 high/low byte 3, 4, 12, 14 reset carry flag 40 symbol 38 (RCF) 5 stacks 18...
  • Page 240 CPU User Manual TMX 40, 190 TRAP 42, 192 traps 34 using extended addressing 39 vector address notation 37 watch-dog timer 194 watch-dog timer refresh 40 WDT 40, 194 working register addressing 16 notation 37 pair notation 37 X 37...

Table of Contents