ZiLOG Z8018 Series User Manual page 61

Table 6. I/O Address Map for Z80180-Class Processors Only (Continued)
Register
INT IL Register (Interrupt Vector Low
Register)
INT/TRAP Control Register
Reserved
Refresh Refresh Control Register
Reserved
MMU MMU Common Base Register
MMU Bank Base Register
MMU Common/Bank Area Register
I/O Reserved
Operation Mode Control Register
I/O Control Register
Family MPU User Manual
Mnemonic Binary
IL XX110011
ITC XX110100
XX110101
RCR XX110110
XX110111
CBR XX111000
BBR XX111001
CBAR XX111010
XX111011
XX111101
OMCR XX111110
ICR XX111111
Z8018x
Address
Hex Page
33H 67
34H 68
35H
36H 88
37H
38H 61
39H 62
3AH 60
3BH
3DH
3EH 15
3FH 42
UM005004-0918
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